Hi,
I am trying to use FPGA to generate digital waveform and send it to AD9102 via SPI.
I have a AD9102 evaluation board right now. I removed XJP 1,3,4,5 to disconnect the SPI communications between microcontroller and AD 9102 and changed the trigger signal to J11 SMA port.
The SPI communication between FPGA and AD 9102 is shown below. The MISO is not used.
FPGA (master) AD9102 (slave)
SPI_CLK => SCLK (on XP3)
MOSI => SDIO1 (on XP3)
SS => CSB (on XP3)
The output signal from FPGA is LVCMOS 3.3V. The SPI signals from FPGA can be decoded correctly on my oscilloscope.
Both the AD9102 eval board and the FPGA have common ground and power supply.
I tried to test the the sample code on this post AD9102: help with /TRIGGER programming .
The trigger signal from a function generator has a falling edge every 1/ 1kHz. The CLKN/P input is from FPGA at 50 MHz. The sequences below are sent to AD9102 via SPI. But I have not got any output from the DAC.
I am not sure whether the problem comes from the register configurations or other parts of the setup. Thank you.
setup_seq[0] <= 32'h00002004; /* SPICONFIG - reset */
setup_seq[1] <= 32'h00000000; /* SPICONFIG */
setup_seq[2] <= 32'h000101c7; /* POWERCONFIG */
setup_seq[3] <= 32'h00020000; /* CLOCKCONFIG */
setup_seq[4] <= 32'h00030000; /* REFADJ */
setup_seq[5] <= 32'h00070000; /* DACAGAIN */
setup_seq[6] <= 32'h00080000; /* DACRANGE */
setup_seq[7] <= 32'h000c000a; /* DACRSET */
setup_seq[8] <= 32'h001e0000; /* PAT_STATUS - STOP */
setup_seq[9] <= 32'h001d0001; /* RAMUPDATE */
setup_seq[10] <= 32'h001f0001; /* PAT_TYPE - finite */
setup_seq[11] <= 32'h0020000e; /* PATTERN_DLY */
setup_seq[12] <= 32'h00258000; /* DACDOF - max negative */
setup_seq[13] <= 32'h00270000; /* WAV_CONFIG - SRAM values */
setup_seq[14] <= 32'h00280111; /* PAT_TIMEBASE */
setup_seq[15] <= 32'h0029000a; /* PAT_PERIOD */
setup_seq[16] <= 32'h002b0001; /* DAC_PAT - 1 time */
setup_seq[17] <= 32'h002c0001; /* DOUT_START */
setup_seq[18] <= 32'h002d0010; /* DOUT_CONFIG */
setup_seq[19] <= 32'h00318000; /* DAC_CST */
setup_seq[20] <= 32'h00354000; /* DAC_DGAIN 0x400=1x */
setup_seq[21] <= 32'h00370007; /* SAW_CONFIG */
setup_seq[22] <= 32'h003e0100; /* DDS_TW32 */
setup_seq[23] <= 32'h003f0000; /* DDS_TW1 */
setup_seq[24] <= 32'h00430000; /* DDS_PW */
setup_seq[25] <= 32'h00440002; /* TRIG_TW_SEL */
setup_seq[26] <= 32'h00450003; /* DDS_CONFIG */
setup_seq[27] <= 32'h00470000; /* TW_RAM_CONFIG */
setup_seq[28] <= 32'h005c0001; /* START_DELAY */
setup_seq[29] <= 32'h005d0000; /* START_ADDR (<<4) */
setup_seq[30] <= 32'h005e0070; /* STOP_ADDR (<<4) */
setup_seq[31] <= 32'h005f0001; /* DDS_CYC */
setup_seq[32] <= 32'h001d0001; /* RAMUPDATE */
setup_seq[33] <= 32'h001e0004; /* PAT_STATUS - MEM_ACCESS ON */
setup_seq[34] <= 32'h001d0001; /* RAMUPDATE */
setup_seq[35] <= 32'h60001000;
setup_seq[36] <= 32'h60010000;
setup_seq[37] <= 32'h60022000;
setup_seq[38] <= 32'h60030000;
setup_seq[39] <= 32'h60043000;
setup_seq[40] <= 32'h60050000;
setup_seq[41] <= 32'h60064000;
setup_seq[42] <= 32'h60070000;
setup_seq[43] <= 32'h001e0000; /* PAT_STATUS - MEM_ACCESS OFF */
setup_seq[44] <= 32'h001d0001; /* RAMUPDATE */
setup_seq[45] <= 32'h001e0001; /* PAT_STATUS - RUN */
