AD9102 FPGA communication

Hi, 

I am trying to use FPGA to generate digital waveform and send it to AD9102 via SPI.

I have a AD9102 evaluation board right now. I removed XJP 1,3,4,5 to disconnect the SPI communications between microcontroller and AD 9102 and changed the trigger signal to J11 SMA port.

The SPI communication between FPGA and AD 9102 is shown below. The MISO is not used.

FPGA (master)                           AD9102 (slave)

SPI_CLK                     =>           SCLK (on XP3)

MOSI                           =>           SDIO1 (on XP3)

SS                               =>            CSB (on XP3)

The output signal from FPGA is LVCMOS 3.3V. The SPI signals from FPGA can be decoded correctly on my oscilloscope.

Both the AD9102 eval board and the FPGA have common ground and power supply.

I tried to test the the sample code on this post AD9102: help with /TRIGGER programming .

The trigger signal from a function generator has a falling edge every 1/ 1kHz. The CLKN/P input is from FPGA at 50 MHz. The sequences below are sent to AD9102 via SPI. But I have not got any output from the DAC.

I am not sure whether the problem comes from the register configurations or other parts of the setup.  Thank you.

setup_seq[0] <= 32'h00002004; /* SPICONFIG - reset */
setup_seq[1] <= 32'h00000000; /* SPICONFIG */
setup_seq[2] <= 32'h000101c7; /* POWERCONFIG */
setup_seq[3] <= 32'h00020000; /* CLOCKCONFIG */
setup_seq[4] <= 32'h00030000;  /* REFADJ */
setup_seq[5] <= 32'h00070000;  /* DACAGAIN */
setup_seq[6] <= 32'h00080000;  /* DACRANGE */
setup_seq[7] <= 32'h000c000a; /* DACRSET */
setup_seq[8] <= 32'h001e0000;  /* PAT_STATUS - STOP */
setup_seq[9] <= 32'h001d0001; /* RAMUPDATE */

setup_seq[10] <= 32'h001f0001; /* PAT_TYPE - finite */
setup_seq[11] <= 32'h0020000e; /* PATTERN_DLY */
setup_seq[12] <= 32'h00258000; /* DACDOF - max negative */
setup_seq[13] <= 32'h00270000; /* WAV_CONFIG - SRAM values */
setup_seq[14] <= 32'h00280111;  /* PAT_TIMEBASE */
setup_seq[15] <= 32'h0029000a;   /* PAT_PERIOD */
setup_seq[16] <= 32'h002b0001;  /* DAC_PAT - 1 time */
setup_seq[17] <= 32'h002c0001; /* DOUT_START */
setup_seq[18] <= 32'h002d0010;  /* DOUT_CONFIG */

setup_seq[19] <= 32'h00318000;  /* DAC_CST */
setup_seq[20] <= 32'h00354000;   /* DAC_DGAIN 0x400=1x */
setup_seq[21] <= 32'h00370007; /* SAW_CONFIG */
setup_seq[22] <= 32'h003e0100;  /* DDS_TW32 */
setup_seq[23] <= 32'h003f0000; /* DDS_TW1 */
setup_seq[24] <= 32'h00430000;  /* DDS_PW */
setup_seq[25] <= 32'h00440002;   /* TRIG_TW_SEL */
setup_seq[26] <= 32'h00450003; /* DDS_CONFIG */
setup_seq[27] <= 32'h00470000;   /* TW_RAM_CONFIG */
setup_seq[28] <= 32'h005c0001;  /* START_DELAY */

setup_seq[29] <= 32'h005d0000;  /* START_ADDR (<<4) */
setup_seq[30] <= 32'h005e0070;   /* STOP_ADDR (<<4) */
setup_seq[31] <= 32'h005f0001;  /* DDS_CYC */
setup_seq[32] <= 32'h001d0001; /* RAMUPDATE */

setup_seq[33] <= 32'h001e0004;  /* PAT_STATUS - MEM_ACCESS ON */
setup_seq[34] <= 32'h001d0001; /* RAMUPDATE */

setup_seq[35] <= 32'h60001000;
setup_seq[36] <= 32'h60010000;
setup_seq[37] <= 32'h60022000;
setup_seq[38] <= 32'h60030000;
setup_seq[39] <= 32'h60043000;
setup_seq[40] <= 32'h60050000;
setup_seq[41] <= 32'h60064000;
setup_seq[42] <= 32'h60070000;

setup_seq[43] <= 32'h001e0000; /* PAT_STATUS - MEM_ACCESS OFF */
setup_seq[44] <= 32'h001d0001;  /* RAMUPDATE */
setup_seq[45] <= 32'h001e0001;  /* PAT_STATUS - RUN */

  • Hi -

    Here is a register value file that will get the AD9102 to produce a CW sine wave.

    Thanks

    example6.regval.zip
  • Hi Larry,

    Thanks for the reply. I have got anything work yet.

    I tried this example. It only work with the microcontroller with the provided GUI.

    I use scope to observe the data from microcontroller to ad9102.

    1. The 32-bit data is transmitted by "SS low => delay => 16-bit address (SPI_CLK on) => delay => 16-bit parameter (SPI_CLK on)  => delay => ss high". I am not sure whether these delays are crucial. But I set them in my FPGA code.

    2. When loading the example 6 regval file, the sequence below was sent from microcontroller to ad9102. The last 2 sequences "setup_seq[94] <= 32'h001e0001; setup_seq[95] <= 32'h001d0001;" are not in your attached sequence. But they seem to be important.

    setup_seq[0] <= 32'h00000000;
    setup_seq[1] <= 32'h00010e00;
    setup_seq[2] <= 32'h00020000;
    setup_seq[3] <= 32'h00030000;
    setup_seq[4] <= 32'h00044000;
    setup_seq[5] <= 32'h00054000;
    setup_seq[6] <= 32'h00064000;
    setup_seq[7] <= 32'h00074000;
    setup_seq[8] <= 32'h00080000;
    setup_seq[9] <= 32'h00091f00;

    setup_seq[10] <= 32'h000a1f00;
    setup_seq[11] <= 32'h000b1f00;
    setup_seq[12] <= 32'h000c1f00;
    setup_seq[13] <= 32'h000d0000;
    setup_seq[14] <= 32'h000e0000;
    setup_seq[15] <= 32'h000f0000;
    setup_seq[16] <= 32'h00100000;
    setup_seq[17] <= 32'h00110000;

    setup_seq[18] <= 32'h00120000;
    setup_seq[19] <= 32'h00130000;
    setup_seq[20] <= 32'h00140000;
    setup_seq[21] <= 32'h00150000;
    setup_seq[22] <= 32'h00160000;
    setup_seq[23] <= 32'h00170000;
    setup_seq[24] <= 32'h00180000;
    setup_seq[25] <= 32'h00190000;
    setup_seq[26] <= 32'h001a0000;
    setup_seq[27] <= 32'h001b0000;

    setup_seq[28] <= 32'h001c0000;

    setup_seq[29] <= 32'h001f0000;
    setup_seq[30] <= 32'h0020000E;
    setup_seq[31] <= 32'h00210000;
    setup_seq[32] <= 32'h00220000;
    setup_seq[33] <= 32'h00230000;

    setup_seq[34] <= 32'h00240000;
    setup_seq[35] <= 32'h00250000;
    setup_seq[36] <= 32'h00261212;
    setup_seq[37] <= 32'h00271232;
    setup_seq[38] <= 32'h00280111;
    setup_seq[39] <= 32'h0029ffff;
    setup_seq[40] <= 32'h002a0101;
    setup_seq[41] <= 32'h002b0101;
    setup_seq[42] <= 32'h002c0003;
    setup_seq[43] <= 32'h002d0000;

    setup_seq[44] <= 32'h002e0000;
    setup_seq[45] <= 32'h002f0000;
    setup_seq[46] <= 32'h00300000;
    setup_seq[47] <= 32'h00310000;
    setup_seq[48] <= 32'h00324000;
    setup_seq[49] <= 32'h00334000;
    setup_seq[50] <= 32'h00344000;
    setup_seq[51] <= 32'h00354000;

    setup_seq[52] <= 32'h00360001;
    setup_seq[53] <= 32'h00377E00;
    setup_seq[54] <= 32'h00380000;
    setup_seq[55] <= 32'h00390000;
    setup_seq[56] <= 32'h003a0000;
    setup_seq[57] <= 32'h003b0000;
    setup_seq[58] <= 32'h003c0000;
    setup_seq[59] <= 32'h003d0000;
    setup_seq[60] <= 32'h003e0750;
    setup_seq[61] <= 32'h003f7500;

    setup_seq[62] <= 32'h00400000;
    setup_seq[63] <= 32'h00410000;
    setup_seq[64] <= 32'h00420000;
    setup_seq[65] <= 32'h00430000;
    setup_seq[66] <= 32'h00440002;
    setup_seq[67] <= 32'h00450000;
    setup_seq[68] <= 32'h00460000;
    setup_seq[69] <= 32'h00470000;

    setup_seq[70] <= 32'h00480000;
    setup_seq[71] <= 32'h00490000;
    setup_seq[72] <= 32'h004a0000;
    setup_seq[73] <= 32'h004b0000;
    setup_seq[74] <= 32'h004c0000;
    setup_seq[75] <= 32'h004d0000;
    setup_seq[76] <= 32'h004e0000;
    setup_seq[77] <= 32'h004f0000;

    setup_seq[78] <= 32'h00502710;
    setup_seq[79] <= 32'h00510000;
    setup_seq[80] <= 32'h00520000;
    setup_seq[81] <= 32'h00530001;
    setup_seq[82] <= 32'h00540000;
    setup_seq[83] <= 32'h00550000;
    setup_seq[84] <= 32'h00560000;
    setup_seq[85] <= 32'h00570001;
    setup_seq[86] <= 32'h00581770;
    setup_seq[87] <= 32'h00590000;

    setup_seq[88] <= 32'h005a0000;
    setup_seq[89] <= 32'h005b0001;
    setup_seq[90] <= 32'h005c0fa0;
    setup_seq[91] <= 32'h005d0000;
    setup_seq[92] <= 32'h005e0000;
    setup_seq[93] <= 32'h005f7FFF;

    setup_seq[94] <= 32'h001e0001;
    setup_seq[95] <= 32'h001d0001;

    3. When pressing the "WRITE ACTIVE TAB", the following sequences are sent. They are not included in the sequence you attached.

    setup_seq[96] <= 32'h00450000;
    setup_seq[97] <= 32'h005d0000;
    setup_seq[98] <= 32'h005e0000;
    setup_seq[99] <= 32'h005c0fa0;
    setup_seq[100] <= 32'h00271232;
    setup_seq[101] <= 32'h001f0000;
    setup_seq[102] <= 32'h002b0101;
    setup_seq[103] <= 32'h00354000;
    setup_seq[104] <= 32'h00250000;
    setup_seq[105] <= 32'h003e0750;

    setup_seq[106] <= 32'h003f7500;
    setup_seq[107] <= 32'h00430000;
    setup_seq[108] <= 32'h00310000;
    setup_seq[109] <= 32'h00377e00;
    setup_seq[110] <= 32'h00470000;
    setup_seq[111] <= 32'h005f7fff;
    setup_seq[112] <= 32'h001d0001;

    I am not sure whether I am using the right sequences, or some other things are wrong. 

  • Hi -

    If you're still working on this, if you used the load register sequence from file button and not the write active tab button you will see all the SPI writes needed to do what you want with the AD9102.

    Thanks