Why is my AD9162 Eval Board not Locking to an external reference clock?

I am trying to control an AD9162-FMCB-EBZ evaluation board using a Xilinx KCU105 evaluation board and an external reference clock.  I have written firmware to control the ADF4355, AD9508, and AD9162 on the evaluation board, but I cannot seem to get the AD9162 to lock to the REFCLK or the SYSREF.  Is there any documentation on what the register settings should be for each part?  I have a 125MHz external reference going into the ADF4355 to generate my DAC clock at 2GHz. 

The AD9162 locks to an external reference through J31, but won't lock tot he clock coming from the ADF4355.  The AD9162 also reports that there is too much jitter on the SYSREF signal (I get this information by reading register x024).

Any suggestions?

Thank you,


  • The User Guide on the ADI Wiki page here: https://wiki.analog.com/resources/eval/dpg/ad916x-fmcx-ebz has detailed instructions for how to use an external clock and/or external reference with the eval board. Please check that page for instructions for how to do this.

    If you use the ACE software, even not connected to the eval board, you can configure the board with your settings, for example 2 GSPS DAC clock, using the wizard, select the "Record Macro" option, click the "apply" button, then select "Stop recording" option. You will have a complete set of register writes necessary for the configuration you chose. You can save that as a .adimacro file for your later use and also to copy those writes into your software.

    There is also the API that can be used, which is ANSI C device drivers that can be compiled into your embedded systems code. The API is linked from the AD9162 product page here: http://www.analog.com/en/design-center/processors-and-dsp/evaluation-and-development-software/AD916x-API.html .

  • Thank you.  I will try to run the ACE software and see where that leads

    me.  I will let you know how it works out.

    On Mon, Jan 23, 2017 at 1:21 PM, danf <

  • I ran the ACE software and I reprogrammed my firmware to generate the same

    register settings, but I am confused by the results.  The ADF4355 looks

    like it is programmed to generate 2280 MHz instead of 2000 MHz.  It also

    looks like the AD9508 is programmed to power-down outputs 1, 2, and 3,

    which are the SYSREF signals.  I don't understand this at all.  Can you

    help to explain?

    I am using a 125 MHz external reference into J61 and I am attempting to set

    up a 2 GHz DAC sampling rate.  The picture below shows my setup.  I tried

    both with the DAC Clock Source as "ADF4355+ADCLK914" and "External Direct

    *** (J31)", but I get the same results either way.

  • If you use the on-board reference and the on-board ADF4355 PLL, are you able to get the board to work? For example, Configuration #2 in the User Guide:


    If so, then you should be able to also get Configuration #1 working if you follow those steps. Note that both J31 and J61 must have the same reference clock. The best way to do this is to have them come from the same signal source. (In fact, J61 can be the internal 10 MHz reference of the J31 clock.) You should also be able to use an external reference into J61 and use the on-board ADF4355. Please remember to remove the jumper on J1 or the on-board reference (120 MHz) will be selected. With the output that you are seeing, I'm suspecting you don't have the correct reference chosen. Can you check those items and report back?

  • Thanks so much for your feedback.  I am out of the office today, but will

    verify those things tomorrow and get back to you.

    Thanks again,


    On Wed, Jan 25, 2017 at 1:22 PM danf <