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Feasibility of LVPECL & LVDS CLK at AD9746

Hello,

My customer use AD9746 at their system and they should use LVPECL or LVDS CLK for this DAC.

And they will use LVPECL clk source.

Below are the voltage swing spec. of AD9746 clock input & clock sources.

1. LVPECL:  0 to 2 V         (1.8VL - 2.2.VH)

2. LVDS:     0.3 to 1.425V  (1.025VL 1.375VH)

3. AD9746

      - Differential : 0.4 to 1.6V

      - Single-ended: 0 to 0.8V

      - Common-Mode: 0.3 to 0.5V

 

Q1) Can AD9746 support LVPECL Clk input?

    Or would you recommend a circuit for supporting LVPECL clk input?

 

Q2) Would you recommend a circuit for supporting LVDS Clk input?

   (Can they use Fig 28 circuit for this directly ?)

Plese advise me.

Regards,

Se-woong

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  • Hello,

    I already got answers about this issue from CIC.ASIA.

    Please refer below answers.

    ------------------------------------------------------------------------------------------------------------

    LVPECL should be a good source for clocking this AD9746 DAC.

    You need to make sure you have enough voltage swing and matches the differential voltage level, If I am not wrong the standard LVPECL specification matches the clock requirement for this DAC.

     

    LVDS signal has lower common mode voltage and swing, so to meet the clock input specification you need to use the clock configuration as mentioned in the datasheet.

     ------------------------------------------------------------------------------------------------------------

     

    Regards,

    Se-woong

Reply
  • Hello,

    I already got answers about this issue from CIC.ASIA.

    Please refer below answers.

    ------------------------------------------------------------------------------------------------------------

    LVPECL should be a good source for clocking this AD9746 DAC.

    You need to make sure you have enough voltage swing and matches the differential voltage level, If I am not wrong the standard LVPECL specification matches the clock requirement for this DAC.

     

    LVDS signal has lower common mode voltage and swing, so to meet the clock input specification you need to use the clock configuration as mentioned in the datasheet.

     ------------------------------------------------------------------------------------------------------------

     

    Regards,

    Se-woong

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