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AD9762 Input data stream bits syncronizing by clock on linux

I implemented AD9762 and FPGA ZYNQ, LINUX(Petalinux). I connect it using AXI-GPIO-12Bits for Input data stream to AD9762. and I do a clcok 1MHz to AD9762.

The Question is arised from this 1Mhz and data stream input control...

I implemented to contorol AXI_GPIO using UIO(User Input/Output). I can read and write infinitely using "for Loop" or "While Loop".

what is more recommanded to syncronize Input data streams and clock(1Mhz).

I thought

1. calculate the time of For Loop(in for loop, write mapping-memory) 

2. re-Design to get a clock edge(1Mhz) also.

Conventinally, the latter is right? If then, How can  I make a confirm that it is precisely syncronized.

I thought, it is some difficult to make confirm.Because I can get a data regardless of the time although any-un-syncronization occurred.

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