I have a AD9162-FMC122-EBZ eval board attached to a Xilinx ZCU102 Ultrascale+ eval board. I created a JESD204B transmitter based on the Xilinx JESD204 sample design. The transmitter and AD9162 are operating in Subclass 0 mode, so SYSREF is not used.
The data link synchronization passes Code Group Synchronization on all 8 lanes and the AD9162 deasserts SYNCOUT.
During the ILAS synchronization phase, the AD9162 also reports successful Frame Sync and ILAS on all 8 lanes, however there are checksum errors on lanes 1, 2, and 6. The eight lane ID status registers are correct EXCEPT for lane 6 (address 0x043A) which is inverted 0x19 (should be 0x06).
The checksum and lane ID errors are the same whether I use ACE or my custom software to configure the AD9162-FMC122-EBZ.
Any thoughts as to what would cause the checksum errors? And why is lane 6 ID inverted?
It sounds like that lane might be inverted in the FPGA. Do the bits [7:5] also appear inverted? Can you check that the correct lane ID is being sent by the FPGA?