Products Mentioned

AD9102 Production
The AD9102 TxDAC and waveform generator is a high performance digital-to-analog converter (DAC) integrating on-chip pattern memory for complex waveform...
Datasheet
AD9102 on Analog.com

Associated Drivers

  • State Verified Answer
  • Replies 3 replies
  • Subscribers 25 subscribers
  • Views 1431 views
  • Users 0 members are here
Options
Related 

        

            Post
             Go back to editing
        

    

    


    

    









		












	
	
			
	
			
		
	
	
		

		
AD9102: help with generator random waveform



		

			

									
					    jsd_ele
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Jul 14, 2017 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    Hi all；
    
 
    I'm having difficulty setting up the AD9102 to output random waveform from the SRAM (it does not work at all!, And we have already generator SIN_WAVE and SAW_WAVE). Here are several question during datasheet;
    
 
    1.About Start_ADDR & Stop_ADDR in generator random waveform;
    
 
       As we known, the ADDR of SRAM is 16bit(0x6000~0x6fff) but Start_ADDR with only 12-bit available,so does it means Start_ADDR occupy 12LSB of the SRAM ADDR;(i've gotten that the DAC_output occupy 12MSB of SRAM_ADDR);
    
 
    2. Here are the C code from the AD9102: help with /TRIGGER programming  
    
 
    SPIbusSet(SPIBUS_DEV_AOM_DAC,0x60001000);
    
 
    SPIbusSet(SPIBUS_DEV_AOM_DAC,0x60010000);
    
 
    SPIbusSet(SPIBUS_DEV_AOM_DAC,0x60022000);
    
 
    SPIbusSet(SPIBUS_DEV_AOM_DAC,0x60030000);
    
 
    SPIbusSet(SPIBUS_DEV_AOM_DAC,0x60043000);
    
 
    SPIbusSet(SPIBUS_DEV_AOM_DAC,0x60050000);
    
 
    SPIbusSet(SPIBUS_DEV_AOM_DAC,0x60064000);
    
 
    SPIbusSet(SPIBUS_DEV_AOM_DAC,0x60070000);
    
 
    what surprising me most is how can it generator random waveform! From date sheet, we were known[15:12]is reserved!!
    
 
    3.Is there any different  in Configuring the some  basic SFR (like SPI_configure) between the generator SIN_WAV and random  waveform .
    
 
    4. Our MCU is the basic 8051(TTL-level instead of 3.3V). We wonder it will bring any side_effect to ad9102?
    
 
    I find the documentation very confusing, so thanks for any input you might have on this.
    
 
    Thanks!
    
 
    Mayer
    
 
     
    
 
     
    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 ad9102
                
                                                    
                 clock and timing
                
                                                    
                 Direct Digital Synthesis (DDS)
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			








	
	
	
	



Parents
	
      
	

    • 
	
      



	
		
	
	



      
	
      
		
      
							
					
      
		
      
			
													0
							
			
				
									
							        
			
			
			
        
            
						
                            
            
            				
            
                on Jul 30, 2017 1:32 PM
            
            
					
        
	
        

		
		
        
					
        
  
        
   
        Hi
        
   
        My schematic is below :
        
   
         
        
   
        But my DAC (AD9102) not work.
        
   
        Please Help me.
        
   
        My code is in attache.
        
   
          0x00000000); /* SPICONFIG */
        
   
          0x000101C7); /* POWERCONFIG */
        
   
          0x00020000); /* CLOCKCONFIG */
        
   
          0x00030000); /* REFADJ */
        
   
          0x00070000); /* DACAGAIN */
        
   
          0x00080000); /* DACRANGE */
        
   
          0x000C000A); /* DACRSET */
        
   
          0x001E0000); /* PAT_STATUS - STOP */
        
   
          0x001D0001); /* RAMUPDATE */
        
   
         
        
   
          0x001F0001); /* PAT_TYPE - finite */
        
   
          0x00200000); /* PATTERN_DLY */
        
   
          0x00258000); /* DACDOF - max negative */
        
   
          0x00270000); /* WAV_CONFIG - SRAM values */
        
   
          0x00280111); /* PAT_TIMEBASE */
        
   
          0x0029000A); /* PAT_PERIOD */
        
   
          0x002B0001); /* DAC_PAT - 1 time */
        
   
          0x002C0001); /* DOUT_START */
        
   
          0x002D0010); /* DOUT_CONFIG */
        
   
          0x00318000); /* DAC_CST */
        
   
          0x00354000); /* DAC_DGAIN 0x400=1x */
        
   
          0x00370007); /* SAW_CONFIG */
        
   
          0x003E0100); /* DDS_TW32 */
        
   
          0x003F0000); /* DDS_TW1 */
        
   
          0x00430000); /* DDS_PW */
        
   
          0x00440002); /* TRIG_TW_SEL */
        
   
          0x00450003); /* DDS_CONFIG */
        
   
          0x00470000); /* TW_RAM_CONFIG */
        
   
          0x005C0000); /* START_DELAY */
        
   
          0x005D0000); /* START_ADDR («4) */
        
   
          0x005E0070); /* STOP_ADDR («4) */
        
   
          0x005F0001); /* DDS_CYC */
        
   
          0x001D0001); /* RAMUPDATE */
        
   
         
        
   
          0x001E0004); /* PAT_STATUS - MEM_ACCESS ON */
        
   
          0x001D0001); /* RAMUPDATE */
        
   
         
        
   
         ,0x60001000);
        
   
         ,0x60010000);
        
   
         ,0x60022000);
        
   
         ,0x60030000);
        
   
         ,0x60043000);
        
   
         ,0x60050000);
        
   
         ,0x60064000);
        
   
         ,0x60070000);
        
   
         
        
   
          0x001E0000); /* PAT_STATUS - MEM_ACCESS OFF */
        
   
          0x001D0001); /* RAMUPDATE */
        
   
          0x001E0001); /* PAT_STATUS - RUN */
        
  
        
 
        
 
         
 
        
 
        
  
         
  
        
 
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

        • 

	
      



Reply

        


      • 
	
        



	
		
	
	



        
	
        
		
        
							
					
        
		
        
			
													0
							
			
				
									
							        
			
			
			
          
            
						
                            
            
            				
            
                on Jul 30, 2017 1:32 PM
            
            
					
          
	
          

		
		
          
					
          
  
          
   
          Hi
          
   
          My schematic is below :
          
   
           
          
   
          But my DAC (AD9102) not work.
          
   
          Please Help me.
          
   
          My code is in attache.
          
   
            0x00000000); /* SPICONFIG */
          
   
            0x000101C7); /* POWERCONFIG */
          
   
            0x00020000); /* CLOCKCONFIG */
          
   
            0x00030000); /* REFADJ */
          
   
            0x00070000); /* DACAGAIN */
          
   
            0x00080000); /* DACRANGE */
          
   
            0x000C000A); /* DACRSET */
          
   
            0x001E0000); /* PAT_STATUS - STOP */
          
   
            0x001D0001); /* RAMUPDATE */
          
   
           
          
   
            0x001F0001); /* PAT_TYPE - finite */
          
   
            0x00200000); /* PATTERN_DLY */
          
   
            0x00258000); /* DACDOF - max negative */
          
   
            0x00270000); /* WAV_CONFIG - SRAM values */
          
   
            0x00280111); /* PAT_TIMEBASE */
          
   
            0x0029000A); /* PAT_PERIOD */
          
   
            0x002B0001); /* DAC_PAT - 1 time */
          
   
            0x002C0001); /* DOUT_START */
          
   
            0x002D0010); /* DOUT_CONFIG */
          
   
            0x00318000); /* DAC_CST */
          
   
            0x00354000); /* DAC_DGAIN 0x400=1x */
          
   
            0x00370007); /* SAW_CONFIG */
          
   
            0x003E0100); /* DDS_TW32 */
          
   
            0x003F0000); /* DDS_TW1 */
          
   
            0x00430000); /* DDS_PW */
          
   
            0x00440002); /* TRIG_TW_SEL */
          
   
            0x00450003); /* DDS_CONFIG */
          
   
            0x00470000); /* TW_RAM_CONFIG */
          
   
            0x005C0000); /* START_DELAY */
          
   
            0x005D0000); /* START_ADDR («4) */
          
   
            0x005E0070); /* STOP_ADDR («4) */
          
   
            0x005F0001); /* DDS_CYC */
          
   
            0x001D0001); /* RAMUPDATE */
          
   
           
          
   
            0x001E0004); /* PAT_STATUS - MEM_ACCESS ON */
          
   
            0x001D0001); /* RAMUPDATE */
          
   
           
          
   
           ,0x60001000);
          
   
           ,0x60010000);
          
   
           ,0x60022000);
          
   
           ,0x60030000);
          
   
           ,0x60043000);
          
   
           ,0x60050000);
          
   
           ,0x60064000);
          
   
           ,0x60070000);
          
   
           
          
   
            0x001E0000); /* PAT_STATUS - MEM_ACCESS OFF */
          
   
            0x001D0001); /* RAMUPDATE */
          
   
            0x001E0001); /* PAT_STATUS - RUN */
          
  
          
 
          
 
           
 
          
 
          
  
           
  
          
 
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

          • 


        


Children
	
        No Data