We are using the AD9117 DAC in our design. The question is regarding SPI communication. We have tied the PINMD/RESET pin to ground. We configure the DAC in the following manner: SPI reset=1, SPI reset=0 and other current configurations. the DAC is used in multiple boards and runs without problems in most of the boards. Some boards show boot up DAC problems wherein the output of the DAC is erratic. We performed SPI readback to all registers in such cases and we see that the reg values keep toggling between 10 and 255, which we find improbable.
We have been able to reproduce this behavior of the DAC by setting bit 4 of Reg 0 (change to 13 bit addressing) to 1.
My question is, is it possible that sometimes the DAC boots with this bit set, although it should be reset as per default.
Another question which I have is, the 13 bit addressing applies to Reg 00 too?
One clarification question, when you say you are doing the SPI reset high to low - do you mean you're writing it via the SPI or pulsing the RESET pin (pin 35)?
This product family (along with the AD9707/6/5/4 and AD9717/6/5/4 families) do not have an automatic power-on reset circuit to force the SPI controller state machine to initialize and populate the registers with default values. If operating in PIN mode the RESET/PINMD pin will be pulled high at all times and the SPI registers will initialize (however this is not your configuration). When operating in SPI mode, the RESET/PINMD pin (35) must be pulsed high in order to start the SPI interface state machine and populate the SPI registers with default values. See the description of this pin in the datasheet: