AD9162 Inconsistent JESD Link Initialization

I am using the AD9162-FMCC-EBZ eval board with the Xilinx KCU105 eval board. The JESD link fails to establish about 90% of the time after initialization and setup, but once it establishes, I get the DAC output I expect. When the link fails to establish, I continually "reset" the entire system (FPGA, Xilinx JESD core, and 9162) until the link establishes. I'm pretty sure all clocks are setup successfully; my sense is that something in the JESD link is marginal.

My startup and initialization process (on power-on and post-reset) is the following:

1. Initialize the onboard ADF4355 to output 5760 MHz. I do not believe this step ever fails.

2. Initialize the onboard AD9508. I do not believe this step ever fails.

3. Initialize the JESD FPGA core. This step involves writing registers to the core and issuing a soft reset. I do not continue past this step until the JESD core informs me that it has successfully reset.

4. Initialize the AD9162. This step involves writing data to all the registers via the SPI interface. 

Here are some other data points:

1. The PLL is locking. I have an LED that lights when locked, and it is always lit

2. The values in registers 0x470, 0x471, and 0x473 contain random values when initialization and setup fails, even from retry to retry.

3. The value in register 0x472 tends to be 0xFF even during a failure to setup correctly. 

4. The values in registers 0x4B0-0x4B7 are random from reset to reset.

So here is my question: What are the most likely causes of the inconsistent initialization, and what are the fixes most likely to work? Which registers should I monitor or modify? Any advice would be appreciated.

  • I had already incorporated the full setup sequence from the ACE hardware into my setup sequence. Doing that solved earlier problems I had but didn't really help with this latest issue.

    This is the workaround I have currently. It "works" but I am still not satisfied, as there seems to be a deeper and more nuanced problem yet to be solved:

    1. Initialize the Xilinx JESD core and confirm that the core successfully exits reset.

    2. Hold the Xilinx JESD core in reset.

    3. Initialize the AD9162 chip (startup sequence, JESD, and NCO) including an initial soft reset.

    4. Release the Xilinx JESD core from reset.

    5. Monitor registers 0x470, 0x471, 0x472, and 0x473. All will have value 0xFF if link initialization is successful.

    6. If any of the above four registers does not have value 0xFF for 100 milliseconds, I have a watchdog process that resets the entire sequence to step 1.

    Using this procedure, I have one 9162 eval board that will initialize successfully within 1 second and another eval board that will take up to 8 seconds to initialize. 

  • Hey Neal,

    I am trying to get AD9164 to reliably output when controlling it through a MATLAB script.  Sometimes it works perfectly as expected, but most of the time it just drops out and cannot output the tone that we want.  Trying to understand what the issue is.

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