I am developing an application based on AD9715, and I came across a strange problem: the real maximum sampling rate of the DAC is much lower than it is described in the datasheet.
Referencing to AD9715 Datasheet Rev. A, I make the DAC work in Pin Mode, control the data inputs and clocks with a FPGA, connect a 16k resistor to FSADJI and FSADJQ, and use ADA4899 in the differential voltage output circuit. I use both I DAC and Q DAC, so the data inputs DB[9 : 0] are time-multiplexed for each DAC, with a DDR format. It works well and the output voltage is accurate when the data inputs DB[9 : 0] for each DAC keep constant or change at a slow rate, which is lower than 400 samples per second. If the sampling rate (I mean the speed in which DB[9 : 0] for each DAC changes) increases, the output voltage (the differential voltage outputted by two ADA4899s) range will rapidly shrink. As a result, if the sampling rate is higher than 200KSMS, the output voltage will tend to be equal to the full-scale voltage, regardless of the digital inputs. That is, the real maximum sampling rate of AD9715 is 200KSMS, which is much lower than 125MSPS, as described in the datasheet.
In order to solve the problem, I have tried the following methods.
Could you please give me some advice about my problem? Sorry for my poor English and thank you so much for your attention.
I have solved the problem on my self! I wrote 0x80 into IRCML register, and then it worked immediately! Now it can generate rectangular wave up to 50MHz. I think that the problem is relevant to the CMLI pin. At first I left the CMLI pin unconnected. And by writing 0x80 into IRCML, I enabled on-chip IRCML. Does it suggest that we should either connect a resistor to CMLI or enable on-chip IRCML, in order to make the chip work well in high-speed? However, I didn't find any clue about that on the datasheet. Perhaps you should have emphasized this point.
Anyway, thank you for paying attention to this question. I hope that no one would come across it again!