Problem with PLL Locked Option in ACE Software for AD9122.

Question

MicheleV 
 
 thank you for your last help regarding ACE software, that solved my connection issue. But now there is problem with PLL Locked option in ACE software.

it should have glow after the successful connection made. but it didn't.

i have given input to boards as below:

1) 
 Power Supply P5(+5V), P6(GND)

2) Signal Source J1(CLOCK IN), Set source to 500MHz, 2dBm output

3) PC 
 USB 
 Cable XP2

4) DSO at 
 
 J3 (DAC1_P) or J8 (DAC2_P)

5) Data Bits D0-D15 , Frame signal and DAC_CLK_IN from FPGA.

the software setting that i have done is given below:

please help me with it.

Thanks and Regards 
 
 Imran

MicheleV · Accepted Answer

A few more questions/comments/debug suggestions: 
 
 For DAC PLL OFF case (checkbox unchecked):
 
 Can you please probe R26 (near the DAC) to see that the DACCLKP/N pins are getting the 500MHz clock for the DAC rate properly. If they are getting the right clock there shouldn't be an issue getting anything out of the DAC as long as it's also getting a DCI clock (probe A2 or B2 on the P1 connector - underside of the board the pins stick out and can be probed, make sure it's 125MHz). 
 
 I noticed from your picture that the jumpers are set to send the DAC output to the back of the board (JP4/JP5 and JP6/JP17) which then goes through a filter and send to the ADL5372 modulator on this board. Are you sending an LO for the modulator to J9? The RF out of the modulator is J6. If you wish to just look at the DAC outputs, please change the JP4/JP5 and JP6/JP17 jumpers to be the outer pads (see image in the quick start guide under the 'Selecting the DAC Outputs' section: AD9122 Evaluation Board Quick Start Guide [Analog Devices Wiki] ). Once the jumpers are changed you can view the DAC output out of J3 and J8. 
 If you finally are able to get an output but it does not look like a sine wave check:
 
 Are you generating the raw data as unsigned binary or two's complement? Set the appropriate setting in the wizard according to how you're generating the data. 
 If the data still doesn't look right, instead send DC data to the part by sending a value of 0x0000 to the Q DAC and 0x7FFF to the I DAC (two's complement setting in the wizard please). Then you can program the on-chip NCO to modulate the DC data to generate a single-tone and you should be able to get an output and it shouldn't require a correct DCI clock. Click on the NCO block and set it up as shown below, then hit 'Close' and 'Apply'. You will see a tone out at ~25MHz out of the DAC output due to where the NCO is located in the digital datapath.

MicheleV · Answer

Glad you got things working. Just to clarify the last point about DC data, I mean that all of the samples going to the I DAC should be 0x7FFF value and all of the samples to the Q DAC should be 0x0000. Then you can program the NCO and it will do a modulation to that DC data and you will see a sine wave out of the DAC. Glad you have fixed the issue. The AD-FMC-ADP is the only FMC adapter board for FMC to DAC evaluation board - it was made specifically for the HS DAC LVDS evaluation boards to work with an FPGA board with an FMC connector.

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Problem with PLL Locked Option in ACE Software for AD9122.

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