Problem with PLL Locked Option in ACE Software for AD9122.

         thank you for your last help regarding ACE software, that solved my connection issue. But now there is problem with PLL Locked option in ACE software.
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it should have glow after the successful connection made. but it didn't.
i have given input to boards as below:
1)  Power Supply P5(+5V), P6(GND)
2) Signal Source J1(CLOCK IN), Set source to 500MHz, 2dBm output
3) PC  USB  Cable XP2
4) DSO at   J3 (DAC1_P) or J8 (DAC2_P)
5) Data Bits D0-D15 , Frame signal and DAC_CLK_IN from FPGA.
 
the software setting that i have done is given below:
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please help me with it.
 
 

Thanks and Regards

Imran
 
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  • Thanks for your response MicheleV

    1) DAC_CLK_IN is DCI clk.

    2) I am not using any pattern generator like DPG2 and DPG downloader. I am generating sinewave pattern using ZC702 FPGA board and attaching AD-DAC-FMC-ADP connector on LPC of FPGA. Using this AD-DAC-FMC-ADP connector i am connecting AD9122-M5372-EBZ evaluation board.

     

    3) I did the same setting as you did in your set up for AD9122 evaluation board and uncheck the enable PLL clock, still PLL Locked is not glowing but i don't have DPG for pattern generation. I am generating pattern using Vivado Xilinx with ZC702 FPGA. 

    I am generating sine and cosine wave with 30MHz output frequency as data_n (16 bits) and data_p (16bits), High Frame signal (Frame_p) for data_p and low frame signal (Frame_n) for data_n. I am generating dac_clk_n (DCI_n) and dac_clk_p (DCI_p) of 200MHz (clk_out1). this is my data pattern generator in FPGA.

    4) I also check the USB connections acquired through the system tab.

    I also uncheck the Enable PLL clocked and checked if anything comes out at DAC output but nothing is coming out.

    The amount of current drawn by 5V is nearly ~1A. 

    The register memory map

    The voltage level at red and black test points.

    TP3-TP4 => 1.79V (~1.8V)

    TP5-TP6 => 1.77V (~1.8V)

    TP9-TP10 => 3.26V (~3.3V)

    TP1-TP2 => 1.79V (~1.8V)

    TP7-TP8 => 3.29V (~3.3V)

Reply
  • Thanks for your response MicheleV

    1) DAC_CLK_IN is DCI clk.

    2) I am not using any pattern generator like DPG2 and DPG downloader. I am generating sinewave pattern using ZC702 FPGA board and attaching AD-DAC-FMC-ADP connector on LPC of FPGA. Using this AD-DAC-FMC-ADP connector i am connecting AD9122-M5372-EBZ evaluation board.

     

    3) I did the same setting as you did in your set up for AD9122 evaluation board and uncheck the enable PLL clock, still PLL Locked is not glowing but i don't have DPG for pattern generation. I am generating pattern using Vivado Xilinx with ZC702 FPGA. 

    I am generating sine and cosine wave with 30MHz output frequency as data_n (16 bits) and data_p (16bits), High Frame signal (Frame_p) for data_p and low frame signal (Frame_n) for data_n. I am generating dac_clk_n (DCI_n) and dac_clk_p (DCI_p) of 200MHz (clk_out1). this is my data pattern generator in FPGA.

    4) I also check the USB connections acquired through the system tab.

    I also uncheck the Enable PLL clocked and checked if anything comes out at DAC output but nothing is coming out.

    The amount of current drawn by 5V is nearly ~1A. 

    The register memory map

    The voltage level at red and black test points.

    TP3-TP4 => 1.79V (~1.8V)

    TP5-TP6 => 1.77V (~1.8V)

    TP9-TP10 => 3.26V (~3.3V)

    TP1-TP2 => 1.79V (~1.8V)

    TP7-TP8 => 3.29V (~3.3V)

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