Thanks and Regards
Thanks and Regards
Thank you for the clearer images. It appears your hardware and software is all set up appropriately except a question about DAC_CLK_IN from the FPGA, do you mean DCI? What is the pattern generator you…
Apologies for the delay - still needing some time to look this over and respond - hoping to do that this week.
A few more questions/comments/debug suggestions:
Thank you for the clearer images. It appears your hardware and software is all set up appropriately except a question about DAC_CLK_IN from the FPGA, do you mean DCI? What is the pattern generator you're attaching the board to, DPG2? DPG3?
I set this up in my lab earlier with the same settings (500MHz clock to J1, looking at the DAC output) and had the following ACE and DPGDownloader settings and the PLL locked fine for me. See screenshots below.
Make sure that the USB control is acquired through the system tab as shown below and that at least the AD9516 is being programmed properly by seeing the DCO clock readback on the DPGDownloader panel reads ~125MHz.
Another debug step could be if you can you try to see if you can get the setup without enabling the PLL?
Just uncheck the 'Enable PLL' setting in ACE and click apply. See if you can get anything out of the DAC at the outputs in this configuration to make sure the board is functional. What is the amount of current that the 5V supply is drawing? It should be ~1A total when the board is powered up and configured properly. Can you show what a 'Read All Registers' displays in the memory map view? You can get to this by double-clicking the AD9122 icon on the board view, then click 'Proceed to Memory Map' on the bottom right corner of the plugin to show the view below.
Can you also check that the voltage rails are all at their appropriate voltage levels? There are red and black test points along the top for each rail that you can measure with a multimeter and make sure they are all correct.
Thank you for the clearer images. It appears your hardware and software is all set up appropriately except a question about DAC_CLK_IN from the FPGA, do you mean DCI? What is the pattern generator you're attaching the board to, DPG2? DPG3?
I set this up in my lab earlier with the same settings (500MHz clock to J1, looking at the DAC output) and had the following ACE and DPGDownloader settings and the PLL locked fine for me. See screenshots below.
Make sure that the USB control is acquired through the system tab as shown below and that at least the AD9516 is being programmed properly by seeing the DCO clock readback on the DPGDownloader panel reads ~125MHz.
Another debug step could be if you can you try to see if you can get the setup without enabling the PLL?
Just uncheck the 'Enable PLL' setting in ACE and click apply. See if you can get anything out of the DAC at the outputs in this configuration to make sure the board is functional. What is the amount of current that the 5V supply is drawing? It should be ~1A total when the board is powered up and configured properly. Can you show what a 'Read All Registers' displays in the memory map view? You can get to this by double-clicking the AD9122 icon on the board view, then click 'Proceed to Memory Map' on the bottom right corner of the plugin to show the view below.
Can you also check that the voltage rails are all at their appropriate voltage levels? There are red and black test points along the top for each rail that you can measure with a multimeter and make sure they are all correct.