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Problem with PLL Locked Option in ACE Software for AD9122.

Imran_Sheikh
on Oct 31, 2017

         thank you for your last help regarding ACE software, that solved my connection issue. But now there is problem with PLL Locked option in ACE software.
Inline image 2
it should have glow after the successful connection made. but it didn't.
i have given input to boards as below:
1)  Power Supply P5(+5V), P6(GND)
2) Signal Source J1(CLOCK IN), Set source to 500MHz, 2dBm output
3) PC  USB  Cable XP2
4) DSO at   J3 (DAC1_P) or J8 (DAC2_P)
5) Data Bits D0-D15 , Frame signal and DAC_CLK_IN from FPGA.
 
the software setting that i have done is given below:
Inline image 3
Inline image 4
 
please help me with it.
 
 

Thanks and Regards

Imran
 
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    •  Analog Employees 
    on Nov 2, 2017 2:36 AM

    Thank you for the clearer images. It appears your hardware and software is all set up appropriately except a question about DAC_CLK_IN from the FPGA, do you mean DCI? What is the pattern generator you're attaching the board to, DPG2? DPG3?

    I set this up in my lab earlier with the same settings (500MHz clock to J1, looking at the DAC output) and had the following ACE and DPGDownloader settings and the PLL locked fine for me. See screenshots below.

    Make sure that the USB control is acquired through the system tab as shown below and that at least the AD9516 is being programmed properly by seeing the DCO clock readback on the DPGDownloader panel reads ~125MHz.

    Another debug step could be if you can you try to see if you can get the setup without enabling the PLL?

    Just uncheck the 'Enable PLL' setting in ACE and click apply. See if you can get anything out of the DAC at the outputs in this configuration to make sure the board is functional. What is the amount of current that the 5V supply is drawing? It should be ~1A total when the board is powered up and configured properly. Can you show what a 'Read All Registers' displays in the memory map view? You can get to this by double-clicking the AD9122 icon on the board view, then click 'Proceed to Memory Map' on the bottom right corner of the plugin to show the view below.

    Can you also check that the voltage rails are all at their appropriate voltage levels? There are red and black test points along the top for each rail that you can measure with a multimeter and make sure they are all correct.

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  • 0
    •  Analog Employees 
    on Nov 2, 2017 2:36 AM

    Thank you for the clearer images. It appears your hardware and software is all set up appropriately except a question about DAC_CLK_IN from the FPGA, do you mean DCI? What is the pattern generator you're attaching the board to, DPG2? DPG3?

    I set this up in my lab earlier with the same settings (500MHz clock to J1, looking at the DAC output) and had the following ACE and DPGDownloader settings and the PLL locked fine for me. See screenshots below.

    Make sure that the USB control is acquired through the system tab as shown below and that at least the AD9516 is being programmed properly by seeing the DCO clock readback on the DPGDownloader panel reads ~125MHz.

    Another debug step could be if you can you try to see if you can get the setup without enabling the PLL?

    Just uncheck the 'Enable PLL' setting in ACE and click apply. See if you can get anything out of the DAC at the outputs in this configuration to make sure the board is functional. What is the amount of current that the 5V supply is drawing? It should be ~1A total when the board is powered up and configured properly. Can you show what a 'Read All Registers' displays in the memory map view? You can get to this by double-clicking the AD9122 icon on the board view, then click 'Proceed to Memory Map' on the bottom right corner of the plugin to show the view below.

    Can you also check that the voltage rails are all at their appropriate voltage levels? There are red and black test points along the top for each rail that you can measure with a multimeter and make sure they are all correct.

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