Problem with PLL Locked Option in ACE Software for AD9122.

If above images is not visible please look at below images

PLL Locked option is not Glowing..

Thank you for the clearer images. It appears your hardware and software is all set up appropriately except a question about DAC_CLK_IN from the FPGA, do you mean DCI? What is the pattern generator you're attaching the board to, DPG2? DPG3?

I set this up in my lab earlier with the same settings (500MHz clock to J1, looking at the DAC output) and had the following ACE and DPGDownloader settings and the PLL locked fine for me. See screenshots below.

Make sure that the USB control is acquired through the system tab as shown below and that at least the AD9516 is being programmed properly by seeing the DCO clock readback on the DPGDownloader panel reads ~125MHz.

Another debug step could be if you can you try to see if you can get the setup without enabling the PLL?

Just uncheck the 'Enable PLL' setting in ACE and click apply. See if you can get anything out of the DAC at the outputs in this configuration to make sure the board is functional. What is the amount of current that the 5V supply is drawing? It should be ~1A total when the board is powered up and configured properly. Can you show what a 'Read All Registers' displays in the memory map view? You can get to this by double-clicking the AD9122 icon on the board view, then click 'Proceed to Memory Map' on the bottom right corner of the plugin to show the view below.

Can you also check that the voltage rails are all at their appropriate voltage levels? There are red and black test points along the top for each rail that you can measure with a multimeter and make sure they are all correct.

Thanks for your response MicheleV

1) DAC_CLK_IN is DCI clk.

2) I am not using any pattern generator like DPG2 and DPG downloader. I am generating sinewave pattern using ZC702 FPGA board and attaching AD-DAC-FMC-ADP connector on LPC of FPGA. Using this AD-DAC-FMC-ADP connector i am connecting AD9122-M5372-EBZ evaluation board.

3) I did the same setting as you did in your set up for AD9122 evaluation board and uncheck the enable PLL clock, still PLL Locked is not glowing but i don't have DPG for pattern generation. I am generating pattern using Vivado Xilinx with ZC702 FPGA. 

I am generating sine and cosine wave with 30MHz output frequency as data_n (16 bits) and data_p (16bits), High Frame signal (Frame_p) for data_p and low frame signal (Frame_n) for data_n. I am generating dac_clk_n (DCI_n) and dac_clk_p (DCI_p) of 200MHz (clk_out1). this is my data pattern generator in FPGA.

4) I also check the USB connections acquired through the system tab.

I also uncheck the Enable PLL clocked and checked if anything comes out at DAC output but nothing is coming out.

The amount of current drawn by 5V is nearly ~1A. 

The register memory map

The voltage level at red and black test points.

TP3-TP4 => 1.79V (~1.8V)

TP5-TP6 => 1.77V (~1.8V)

TP9-TP10 => 3.26V (~3.3V)

TP1-TP2 => 1.79V (~1.8V)

TP7-TP8 => 3.29V (~3.3V)

I also check the yellow test points TP13, TP14, TP15 . there no output across these test points.

At point JP15 and JP10  in DSO (AC coupling)  sine wave is coming out.

At point JP15 and JP10 in DSO (DC coupling) sine wave with DC level is coming out.

the point JP15 and JP10 on evaluation board schematic is REFCK_P and REFCK_N respectively.

Hello MicheleV

   Waiting for reply....