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Problem with PLL Locked Option in ACE Software for AD9122.

         thank you for your last help regarding ACE software, that solved my connection issue. But now there is problem with PLL Locked option in ACE software.
Inline image 2
it should have glow after the successful connection made. but it didn't.
i have given input to boards as below:
1)  Power Supply P5(+5V), P6(GND)
2) Signal Source J1(CLOCK IN), Set source to 500MHz, 2dBm output
3) PC  USB  Cable XP2
4) DSO at   J3 (DAC1_P) or J8 (DAC2_P)
5) Data Bits D0-D15 , Frame signal and DAC_CLK_IN from FPGA.
 
the software setting that i have done is given below:
Inline image 3
Inline image 4
 
please help me with it.
 
 

Thanks and Regards

Imran
 
  • If above images is not visible please look at below images

    PLL Locked option is not Glowing..

  • Thank you for the clearer images. It appears your hardware and software is all set up appropriately except a question about DAC_CLK_IN from the FPGA, do you mean DCI? What is the pattern generator you're attaching the board to, DPG2? DPG3?

    I set this up in my lab earlier with the same settings (500MHz clock to J1, looking at the DAC output) and had the following ACE and DPGDownloader settings and the PLL locked fine for me. See screenshots below.

    Make sure that the USB control is acquired through the system tab as shown below and that at least the AD9516 is being programmed properly by seeing the DCO clock readback on the DPGDownloader panel reads ~125MHz.

    Another debug step could be if you can you try to see if you can get the setup without enabling the PLL?

    Just uncheck the 'Enable PLL' setting in ACE and click apply. See if you can get anything out of the DAC at the outputs in this configuration to make sure the board is functional. What is the amount of current that the 5V supply is drawing? It should be ~1A total when the board is powered up and configured properly. Can you show what a 'Read All Registers' displays in the memory map view? You can get to this by double-clicking the AD9122 icon on the board view, then click 'Proceed to Memory Map' on the bottom right corner of the plugin to show the view below.

    Can you also check that the voltage rails are all at their appropriate voltage levels? There are red and black test points along the top for each rail that you can measure with a multimeter and make sure they are all correct.

  • Thanks for your response MicheleV

    1) DAC_CLK_IN is DCI clk.

    2) I am not using any pattern generator like DPG2 and DPG downloader. I am generating sinewave pattern using ZC702 FPGA board and attaching AD-DAC-FMC-ADP connector on LPC of FPGA. Using this AD-DAC-FMC-ADP connector i am connecting AD9122-M5372-EBZ evaluation board.

     

    3) I did the same setting as you did in your set up for AD9122 evaluation board and uncheck the enable PLL clock, still PLL Locked is not glowing but i don't have DPG for pattern generation. I am generating pattern using Vivado Xilinx with ZC702 FPGA. 

    I am generating sine and cosine wave with 30MHz output frequency as data_n (16 bits) and data_p (16bits), High Frame signal (Frame_p) for data_p and low frame signal (Frame_n) for data_n. I am generating dac_clk_n (DCI_n) and dac_clk_p (DCI_p) of 200MHz (clk_out1). this is my data pattern generator in FPGA.

    4) I also check the USB connections acquired through the system tab.

    I also uncheck the Enable PLL clocked and checked if anything comes out at DAC output but nothing is coming out.

    The amount of current drawn by 5V is nearly ~1A. 

    The register memory map

    The voltage level at red and black test points.

    TP3-TP4 => 1.79V (~1.8V)

    TP5-TP6 => 1.77V (~1.8V)

    TP9-TP10 => 3.26V (~3.3V)

    TP1-TP2 => 1.79V (~1.8V)

    TP7-TP8 => 3.29V (~3.3V)

  • I also check the yellow test points TP13, TP14, TP15 . there no output across these test points.

    At point JP15 and JP10  in DSO (AC coupling)  sine wave is coming out.

    At point JP15 and JP10 in DSO (DC coupling) sine wave with DC level is coming out.

    the point JP15 and JP10 on evaluation board schematic is REFCK_P and REFCK_N respectively.

  • Apologies for the delay - still needing some time to look this over and respond - hoping to do that this week.

  • Hello MicheleV 

                          Its good to hear from you. you can take time but please try to complete as early as possible.

  • A few more questions/comments/debug suggestions:

    • For DAC PLL OFF case (checkbox unchecked):
      • Can you please probe R26 (near the DAC) to see that the DACCLKP/N pins are getting the 500MHz clock for the DAC rate properly. If they are getting the right clock there shouldn't be an issue getting anything out of the DAC as long as it's also getting a DCI clock (probe A2 or B2 on the P1 connector - underside of the board the pins stick out and can be probed, make sure it's 125MHz).
    • I noticed from your picture that the jumpers are set to send the DAC output to the back of the board (JP4/JP5 and JP6/JP17) which then goes through a filter and send to the ADL5372 modulator on this board. Are you sending an LO for the modulator to J9? The RF out of the modulator is J6. If you wish to just look at the DAC outputs, please change the JP4/JP5 and JP6/JP17 jumpers to be the outer pads (see image in the quick start guide under the 'Selecting the DAC Outputs' section: AD9122 Evaluation Board Quick Start Guide [Analog Devices Wiki] ). Once the jumpers are changed you can view the DAC output out of J3 and J8.
    • If you finally are able to get an output but it does not look like a sine wave check:
      • Are you generating the raw data as unsigned binary or two's complement? Set the appropriate setting in the wizard according to how you're generating the data.
      • If the data still doesn't look right, instead send DC data to the part by sending a value of 0x0000 to the Q DAC and 0x7FFF to the I DAC (two's complement setting in the wizard please). Then you can program the on-chip NCO to modulate the DC data to generate a single-tone and you should be able to get an output and it shouldn't require a correct DCI clock. Click on the NCO block and set it up as shown below, then hit 'Close' and 'Apply'. You will see a tone out at ~25MHz out of the DAC output due to where the NCO is located in the digital datapath.
  • Hello MicheleV

    Thanks

    This time  I got some output but it is not look like sinewave. I also tried to generate raw data using binary and two's complement. 

     I don't understand this statement "If the data still doesn't look right, instead send DC data to the part by sending a value of 0x0000 to the Q DAC and 0x7FFF to the I DAC (two's complement setting in the wizard please)." please clarify.

    I changed the jumpers JP4/JP5 and JP6/JP17 jumpers to be the outer pads.

    1) without giving input to DAC i got sine wave

    2)with giving sinewave in binary i got this

    DCI frequency at probe A2 or B2 on the P1 connector is 125MHz

     

    and at R26 near the DAC i got 500MHz

     

    at 500MHz DAC clk , 1) what should be the data rate for DAC input?

                                         2) how to configure ACE software?

     

    Thanks and Regards

    Imran

  • Hello MicheleV

    I configured the DAC correctly. as shown below it gives me output of sinewave of 1GHz

    without giving any input to DAC.

    but I am unable to get the clear sine wave when i feed the data points with 15 MHz

    I got disturbed wave with ~15MHz.

    Please help me with it i didn't know whats happening?

    Thanks and Regards

    Imran Sheikh