AD9715 latency

Hi,

how can I make the DAC latency known and deterministic?

I also need that the latency does not vary in time.

Thanks a lot.

Alberto

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  • 0
    •  Analog Employees 
    on Nov 27, 2017 10:23 PM over 2 years ago

    There is information in the datasheet regarding making the timing deterministic. Please see the "Estimating the Overall DAC Pipeline Delay" section of the datasheet. There is a slight update in process needed for this section which I have copied and corrected below along with a figure in the diagram to determine the correct amount of expected latency out of the DAC, however the theory behind how the DAC should be configured if deterministic latency is needed is still accurate in the current datasheet. The next revision of the datasheet will have the update below included.

    Updated section to be included in the next revision of the datasheet:

    Estimating the Overall DAC Pipeline Delay

    DAC pipeline latency is affected by the phase of the RETIMER-CLK that is selected. If latency is critical to the system and must be constant, the retimer should be forced to a particular phase and not be allowed to automatically select a phase each time.

    Consider the case in which DCLKIO = CLKIN (that is, in phase), and the RETIMER-CLK is forced to Phase 2. Assume that IRISING is 1 (that is, I data is latched on the rising edge and Q data is latched on the falling edge). Then the latency to the output for the I channel is four clock cycles total; one clock cycle from the input interface (D-FF 1, not D-FF0 as it latches data on either edge and does not cause any delay), two clock cycles from the retimer (D-FF 2 and D-FF 4, but not D-FF 3 because it is latched on the half clock cycle or 180°) and one clock cycle going through the analog core (D-FF 5). The latency to the output for the Q channel from the time the falling edge latches it at the pads in D-FF 0 is 3.5 clock cycles (no delay due to D-FF0, 1 clock cycle due to D-FF 1, ½ clock cycle to D-FF 2, 1 clock cycle to D-FF 4, and 1 clock cycle to D-FF 5). This latency for the AD9714/AD9715/AD9716/AD9717 is case specific and needs to be calculated based on the RETIMER-CLK phase that is automatically selected or manually forced.

     

     

    Figure 94. Simplified Diagram of AD9714/AD9715/AD9716/AD9717 Timing

    (I seem to be having issues uploading the image to this thread. The edits done were to add another flip-flop after the current D-FF 0 before going into the Retimer-Clk block so there are currently now 6 flip-flops in the image, D-FF 0 through D-FF 5. D-FF and D-FF 1 are at the input, D-FF 2, D-FF 3 and D-FF 4 are in the retimer-clk block, and D-FF 5 is in the analog DAC core.

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  • 0
    •  Analog Employees 
    on Nov 27, 2017 10:23 PM over 2 years ago

    There is information in the datasheet regarding making the timing deterministic. Please see the "Estimating the Overall DAC Pipeline Delay" section of the datasheet. There is a slight update in process needed for this section which I have copied and corrected below along with a figure in the diagram to determine the correct amount of expected latency out of the DAC, however the theory behind how the DAC should be configured if deterministic latency is needed is still accurate in the current datasheet. The next revision of the datasheet will have the update below included.

    Updated section to be included in the next revision of the datasheet:

    Estimating the Overall DAC Pipeline Delay

    DAC pipeline latency is affected by the phase of the RETIMER-CLK that is selected. If latency is critical to the system and must be constant, the retimer should be forced to a particular phase and not be allowed to automatically select a phase each time.

    Consider the case in which DCLKIO = CLKIN (that is, in phase), and the RETIMER-CLK is forced to Phase 2. Assume that IRISING is 1 (that is, I data is latched on the rising edge and Q data is latched on the falling edge). Then the latency to the output for the I channel is four clock cycles total; one clock cycle from the input interface (D-FF 1, not D-FF0 as it latches data on either edge and does not cause any delay), two clock cycles from the retimer (D-FF 2 and D-FF 4, but not D-FF 3 because it is latched on the half clock cycle or 180°) and one clock cycle going through the analog core (D-FF 5). The latency to the output for the Q channel from the time the falling edge latches it at the pads in D-FF 0 is 3.5 clock cycles (no delay due to D-FF0, 1 clock cycle due to D-FF 1, ½ clock cycle to D-FF 2, 1 clock cycle to D-FF 4, and 1 clock cycle to D-FF 5). This latency for the AD9714/AD9715/AD9716/AD9717 is case specific and needs to be calculated based on the RETIMER-CLK phase that is automatically selected or manually forced.

     

     

    Figure 94. Simplified Diagram of AD9714/AD9715/AD9716/AD9717 Timing

    (I seem to be having issues uploading the image to this thread. The edits done were to add another flip-flop after the current D-FF 0 before going into the Retimer-Clk block so there are currently now 6 flip-flops in the image, D-FF 0 through D-FF 5. D-FF and D-FF 1 are at the input, D-FF 2, D-FF 3 and D-FF 4 are in the retimer-clk block, and D-FF 5 is in the analog DAC core.

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