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How to convert 12 bits Serial LVDS to parallel 12 bits for DAC interface?



		

			

									
					    Karim_Sayed
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Dec 10, 2017 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    I have an FPGA that will give 12-bits output serial LVDS data. I need to convert this data to analog using 12-bits DAC. However, I cannot find suitable serial 12 bit DAC (>100 MHz) signal. (I want to avoid Ball Packages) Is there any possibility to use a deserializer in between? Or if there is another way, as I am also having difficulty finding a proper 12-bit deserializer?? 
    
								
    

				
				
		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    


	















    
	
    
	
    
					



			








	
	
	
	



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                on Feb 8, 2018 1:35 AM
            
            
					
        
	
        

		
		
        
					
        Dear Mr. Deljones,
        
 
        I am using the parallel input DAC (AD9706). My FPGA is giving a serial output which am converting to parallel digital inputs for the DAC using an intermediate De-Serializer. The de-serializer gives a clock output based on the frequency of the serial input it takes from the FPGA. 
        
 
        Now my question is, the clock input for the DAC would be taken from the FPGA or from the clock output of the De-Serializer?
        
 
        Thanks,
        
 
        Karim
        
			
        

		
		
		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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													0
							
			
				
									
							        
			
			
			
          
            
			                            
                        
                on Feb 8, 2018 1:35 AM
            
            
					
          
	
          

		
		
          
					
          Dear Mr. Deljones,
          
 
          I am using the parallel input DAC (AD9706). My FPGA is giving a serial output which am converting to parallel digital inputs for the DAC using an intermediate De-Serializer. The de-serializer gives a clock output based on the frequency of the serial input it takes from the FPGA. 
          
 
          Now my question is, the clock input for the DAC would be taken from the FPGA or from the clock output of the De-Serializer?
          
 
          Thanks,
          
 
          Karim
          
			
          

		
		
		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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