AD9712 phase mismatch between DAC0 and DAC1

Hi !

I have a problem with DAC phase of 2 DAC channels (DAC0 and DAC1) in AD917x-FMC-EBZ board (AD9172 version). In my test, I configure DAC0 out as real channel and DAC1 as imagine channel using output modular switch (AD9712 datasheet pg.60). In this case, I thinks data output of DAC0 and DAC1 must difference 90° in phase. But real output not as expected. My system setting as below.

Test condition:

•      LINK LAYER
  •       JESD204B, Subclass1. SYSREF ON. AC mode
  •       JESD mode 1: L=2, M= 4, F=4, N=16. SCR off.
  •       Lane Rate : 10.240 GBPS
•      DATA PATH:
  •       Input:
    •       Input data rate : 256 MHz
    •       Baseband Frequency : 0
  •      Channel path
    •      Channel interpolation : 6
    •      Channel NCO frequency : 100MHz to 300 MHz
    •      NCO integer mode.
    •      Phase offset : 0
    •      Input Gain :
      •      Channel 1: 2048
      •      Channel 2: 0
      •      Channel 3: 0
      •      Channel 4: 2048
      •      Channel 5: 0
      •      Channel 6: 0
    •      MAIN PATH :
      •     Interpolation : 8
      •      Modulator Switch : Mode2 (DAC0_I to DAC0 core , DAC0_Q to DAC1 core)
      •      NCO frequency (not need but setting to 100MHz)
    •      MESASURE equipment:
      •      Oscilloscope RTM2054 of ROHDE and SCHWARS ( 5 GSPs – 500 MHz)
      •      Probe: SMA Cable with SMA to BNC adaptor, 50Ω, Frequency up to 10 GHz

Result:

It seems DAC0 and DAC1 phase is changed depend on output signal frequency.

Please help me check out why phase between DAC0 and DAC is not 90°. AD9172 characteristic or analog path in EVM board or other problem.

@ I using Modulator Switch is mode 2 to ensure no mismatch between data path of DAC0 and DAC1 can affect this test.

Best regards!

Hoang