My question is about the PLL VCO N0 divider of the AD9146 DAC. In the data sheet (Rev.A page 22. PLL Control register 0x0D) are listed possible values for the N0 as 1, 2, 4 and 4. Is 4 realy the maximum value of N0 or just a typo? Could it be 8?
My problem is, i have a data rate of 40 MSPS. With the x4 interpolation it will rise to 160 MSPS. I will need a DACCLK of 160MHz, but the internal VCO frequency depends on the N0*DACCLK. The possible VCO frequency is from 1GHz to 2.1GHz. With N0 as 4 it will not be possible. (we use the REFCLK pins as clock input)
Is N0 divider 8 possible or do I have to double the data rate at the input or use the DACCLK pins directly instead of REFCLK?
The N0 divider maxes out at /4 (the data sheet is accurate) so you will need to apply one of the other means to achieve the desired DACCLK frequency.