A few questions about AD9164-FMCB-EBZ Evaluation Board

       We purchased AD9164-FMCB-EBZ Evaluation Board and ADS7-v2EBZ Board. When we used them to evaluate the performance of AD9164, we have encountered some problems.

1.The data we tested was inconsistent with the data given in the data sheet. For example, we use DC test mode to get the 2 GHZ , but the 3 GHZ image frequency(about -20 dBc) is much bigger than figure 16 of page 16. I I would like to know why.(we already config AD9164 like the data sheet said)

2.In the Table 9, it shows when FIR85 enable, single tone, fdac = 5 GSPS, we can get a 4 GHZ output with -60 dBc SFDR. I wonder the 4 GHZ is from the NCO or the DPG? What is the magnitude of 4 GHZ?  What is the magnitude of 1 GHZ?

3.when we use 6 GHZ as AD9164’s clock, the interpolation must be bigger than 3 , so the Data Rate will be less than 2 GHZ. Are we right? If we are ,what’s the advantage of it considering we can get 5 GHZ Data Rate when we use 6 GHZ as AD9164’s clock.

Looking forward to your reply, thank you !

  • 1. the data measure for the datasheet are taken based on lab-specific boards. We use these boards to characterize our products. These boards are optimized to reveal full performance of the DAC, for instance. For example, on the eval board we are using more complicated input clock circuit to give the user the options of using on-board clock source or external clock source. this degrades the phase noise of the input clock and adds spurs at the output spectrum. While on our lab boards we use a very clean external clock supply to just measure the performance of the DAC. The example you brought us is also falling in this category. Due to a clock imbalance at the clock input, the spur that you see in your experiment is much worse. Try to play with CLK_DUTY, CLK_CRS_CTRL, and PLL_REF_CLK_PD to get better performance. These registers compensate for some of internal clock receiver imbalance but the major source of imbalance which is the clock source circuit (the balun for example) can't be compensated for. A custom designed board with an optimized clock circuit will resolve the issue.

    2. It's been measured in NCO-only mode and IOUTFS = 40 mA is used. so, according to the datasheet, close to 4.5dBm power is measured at these frequencies

    3. Data Rate is the rate the data coming out of JESD link. If you use higher interpolation filters, you can make sure the image is sitting further from the signal.