I'm not sure if this is the preferred way of reporting documentation errors.The AD9129 datasheet (Rev A and B) lists the IRQ Request 0 register as read only access in table 22. It should however be R/W as shown for example in table 17.
Best regards, David
Thank you for pointing out - reg 0x05 is a status registers, and should have been marked as read-only in table 17.
thank you for your response. I think the register is writeable, as the text on page 47 suggests so: "To clear an IRQ, it is necessary to write a 1b to the bit in Register 0x05 or Register 0x06 that caused the interrupt."This is also the behavior I observe on real hardware.
Thank you again! An interesting way to reset an IRQ. And thank you for confirming it is true in hardware. Will be reflected in revC for sure.