AD9161 SYSREF_PHASE Register

Hi

I'd like to know the detail of the thermometer code in Register 0x037, Bits[7:0] and Register 0x038, Bits[3:0]. For example, when SYSREF_PHASE[11:0] is read as 0xF80, what does the phase of the (DAC clock) divided by 4 mean?

Regards,

Hiroyuki

  • +1
    •  Analog Employees 
    on Jun 4, 2018 5:48 PM

    Since there are just 4 different states of for the SYSREF signal (4 DAC clock positive edges are used to sample SYSREF), only 4 bits of the SYSREF_PHASEx are used to report SYSREF phase state. According to the datasheet register 0x037[7:0] is reporting the state:

     

     

    If the above assumption is correct the following can be interpreted from the SYSREF_PHASEx registers:

    1111-1110-0000 ==> rising edge of SYSREF is sampled at 0x DAC clock cycle delay with reference to the rising edge of divide-by-4 clock

    1111-1100-0000 ==> rising edge of SYSREF is sampled at 1x DAC clock cycle delay with reference to the rising edge of divide-by-4 clock

    1111-1000-0000 ==> rising edge of SYSREF is sampled at 2x DAC clock cycle delay with reference to the rising edge of divide-by-4 clock

    1111-0000-0000 ==> rising edge of SYSREF is sampled at 3x DAC clock cycle delay with reference to the rising edge of divide-by-4 clock

    So, 0xF80 value for SYSREF_PHASE can be translated as "rising edge of SYSREF is sampled at 2x DAC clock cycle delays with reference to the rising edge of divide-by-4 clock"

  • Hi,

    In my system fpga xilinx us+ and ad9164 the sysref is distributed by ad9508 such us the evb. I read the 0x37 and 0x38 registers and the value obtained are fc0, fe0 or f80 (after different power on). Are these values goods for subclass 1 sync or there an elevated jitter? Could I use this sysref signal to sync the LMFC timing? What is the meaning of the jitter window register? Do you know if there is a correspondent register in the xilinx IP block? Thanks in advance.

    Best regards.