We are designing a FPGA to generate a 200MHz bandwidth signal and output it to Fout 2.6GHz.
JESD204B is set to 6 GSPS, and the FPGA sampling rate is 491.52 MHz.
How many MHz should Sysref and CLK be set to?
There is no Matlab. ^^

• Hi miney,

Thanks for reaching out. Before determining what SYSREF frequency should be used, we need to determine your DAC CLK frequency (I presume you are asking about fDAC when you refer to “CLK” frequency). fDAC is determined by the data rate of your JESD204B link as well as the interpolation factor set in your AD9163. You claim that your JESD link is operating at 6 GSPS, but such a data rate is impossible. Even if we assume max data rate JESD parameters (8 lanes with an interpolation factor of 1), we see that your lane rate is:

Lane Rate = 6 GSPS * 16 bits/sample * 10b/8b * 1/8 Lanes = 15 Gbps

Your lane rate of 15 Gbps violates the maximum JESD204B lane rate spec of 12.5 Gbps. Perhaps you made a typo when you noted that your JESD204B data rate was 6 GSPS?

Regarding your question on SYSREF, the SYSREF period T_SYSREF must be satisfy the criteria T_SYSREF > (4*T_DAC + t_SYSS + t_SYSH) where T_DAC is the DAC clock period, t_SYSS is the minimum setup time, and t_SYSH is the minimum hold time. Refer to Table 6 and Figure 2 in the AD9163 datasheet for more detailed information.

Let me know if you have any questions!

echaykov

The CLK in question is fDAC correct, and 6 GSPS is the Lane Rate value.

If the clock design is K(32), L(2), M(2), F(2), S(1), DataRate 307.2MHz, Lane Rate = 6.144GSPS.

1. If you use NCO under the above conditions, can you control fout between 0 and 3.072 GHz?
2. I know that with interpolation, only 80% of the actual bandwidth can be used by the filter.
3. Based on the above conditions, which is more efficient, AD9163 or AD9171?

Thank you~

• Hi miney,

Thanks for the additional details. One slight but important detail to note are the units used for lane rate measurements. You stated that your data rate is 307.2 MHz while your lane rate is 6.144 GSPS (Giga-samples-per-second). Technically speaking, your lane rate is NOT 6.144 GSPS—it is 6.144 Gbps (Giga-bits-per-second). Gbps and GSPS are NOT equivalent units since you are using 16-bits per sample, and each sample is further increased in length due to 8b/10b encoding.

Regarding your most recent set of questions:

1. It depends on what you mean by “fout”. I will assume that “fout” is the same as “fNCO” in this case. The AD9163’s ability to generate a 0 Hz to 3.072 GHz NCO output depends on your data rate, interpolation factor, and FIR85 filter setting. When the FIR85 filter is disabled, -fDAC/2 < fNCO < fDAC/2. Thus, when the FIR85 filter is disabled, it is impossible to set fNCO = 3.072 GHz even if you went to the maximum of fDAC = 6 GHz. When the FIR85 filter is enabled, 0 Hz < fNCO < fDAC. Thus, when the FIR85 is enabled, it is possible to set fNCO = 3.072 GHz, assuming that you choose an appropriate fDAC. If your input data rate is 307.2 MHz and FIR85 is enabled, then you will need an interpolation factor of 12x, 16x, or 24x to generate fNCO = 3.072 GHz. Note that NCO aliases may begin to encroach on your target signal as you approach the limits of the NCO frequency ranges. If you do not want to use the FIR85 filter, you can still cover the same frequency span by utilizing mix mode on the output, but such an implementation is more challenging and requires some workarounds. Refer to Pages 53-55 in the AD9163 datasheet for additional details on the part’s NCO feature.
2. The AD9163 features both 80% and 90% bandwidth filters for interpolation. Using 90% filters will mean that you have more usable bandwidth, but 90% filters will consume more power than their 80% counterparts. Refer to Pages 50-53 in the AD9163 datasheet for additional details on digital filtering.

Let me know if you have any additional questions!

echaykov

Lane rate is 6.144Gbps.

1. The fout to be used is from 836MHz to 2.645GHz, so there is no need to use an interpolation filter. fDAC is 6.144GHz.

2. It is not considered because it does not use an interpolation filter.

3.AD9171 is 6.2Gbps 2ch dac. We need 6.144Gbps processing, so both AD9171 and AD9163 can be used, and the price is not a big deal.

• Hi miney,

Happy to help! While we are on the same page when it comes to GSPS vs. Gbps, it appears that there is still some confusion over the connection between lane rate, data rate, interpolation, and DAC rate.

Based on what you have told me, you have a lane rate of 6.144 Gbps, which translates to a 307.2 MHz data rate. You will be bypassing interpolation but still plan to achieve a DAC rate of 6.144 GHz with an output ranging from 836 MHz to 2.645 GHz. These system settings are impossible to achieve with the AD9163, and I will now walk through the math to illustrate why these settings are unachievable. Earlier, you stated that your JESD link parameters are L = 2 and M = 2. With a 6.144 Gbps lane rate, we can determine your data rate:

Data Rate = 6.144 Gbps * 8/10 * 1 sample/16 bits * 2 lanes/2 converters = 307.2 MHz (or 307.2 MSPS)

Your data rate is 307.2 MHz, meaning that your JESD link is transmitting 307.2 MSPS. Without interpolation (aka an interpolation factor of 1x), we have a data stream of 307.2 MSPS going directly to our DAC. Thus, the DAC rate is:

DAC Rate = 307.2 MHz * 1 = 307.2 MHz

Without any interpolation, our DAC rate must be the same as our data rate. Thus, a 6.144 GHz DAC clock is impossible given your JESD link parameters, lane rate, and interpolation factor. In theory, you could run 307.2 MHz data at 6.144 GHz, but such a configuration is not recommended and may lead to many issues. In order to increase your DAC rate, you will need to interpolate your data, increase your lane rate, or increase the number of lanes used in the JESD link. For instance, if we interpolate by a factor of 16x, our new DAC rate would be:

New DAC Rate = 307.2 MHz * 16 = 4.9152 GHz

Note that the minimum maximum DAC rate is 6 GHz according to the AD9163 datasheet. What this statement means is that we guarantee a maximum DAC rate of 6 GHz. Depending on your operating conditions, you may be able to achieve a 6.144 GHz or higher DAC rate, but it is also possible that only a 6 GHz DAC rate will be achievable. Refer to Tables 1 and 2 in the AD9163 datasheet for more detail.

Bandwidth is also a key consideration when determining input data rate. If you want to generate a signal from 836 MHz to 2.645 GHz, you will need 1.809 GHz of bandwidth, yet your input signal has only 614.4 MHz of bandwidth (307.2 MHz * 2 since you are using complex data).