AD9154 : about RF CLOCK DIVIDER

Hello,

I have two questions about AD9154 from our customer.

1. About register 0x080[0] "RF_CLKDIV_EN"
    In AD9154 datasheet(Rev.C) page-98 the there is "RF_CLKDIV_EN"explanation.
    "Enable RF Clock Divider. The RF clock divider divides the input clock by 2 and provides the result to the DAC for sampling."
    The customer wants to know which function block is set by this register.
    Figure 47 and Figure 78 has divider(1/2) function but there are fixed divide ratio, not disabling.
    Could you please teach me which is the function block to be set by 0x080 RF_CLKDIV_EN bit ?

2. About ACE plug-in
    When using AD9154-FMC-EBZ we use with ACE and ADS7 or ADS8 and following figure is ACE interface for AD9154-FMC-EBZ.


    When I check the box of DAC PLL,  "Fin:" is available.
    Could you please teach me what parameter to be set to "Fin" ?


Best regards,
y-suzuki



I corrected some words.
[edited by: y_suzuki at 2:55 PM (GMT 0) on 23 Jun 2020]
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