Hello,I have two questions about AD9154 from our customer.1. About register 0x080 "RF_CLKDIV_EN" In AD9154 datasheet(Rev.C) page-98 the there is "RF_CLKDIV_EN"explanation. "Enable RF Clock Divider. The RF clock divider divides the input clock by 2 and provides the result to the DAC for sampling." The customer wants to know which function block is set by this register. Figure 47 and Figure 78 has divider(1/2) function but there are fixed divide ratio, not disabling. Could you please teach me which is the function block to be set by 0x080 RF_CLKDIV_EN bit ?2. About ACE plug-in When using AD9154-FMC-EBZ we use with ACE and ADS7 or ADS8 and following figure is ACE interface for AD9154-FMC-EBZ.
When I check the box of DAC PLL, "Fin:" is available. Could you please teach me what parameter to be set to "Fin" ?Best regards,y-suzuki
Yes, good point. I corrected this. "FIN" is the "input frequency into J1"
For #1, the divider is not related to the SERDES PLL at all (Figures 47 and 48). If using the DACCLK PLL please refer to Figure 78. However, RF_CLKDIV_EN is not related: it enables a divider that is connected between the DACCLK pins and the DAC core, when bypassing the DACCLK PLL.
For #2, you can leave Fin at default. Please refer to https://wiki.analog.com/resources/eval/dpg/ad9154-ace-fmc-ebz
to follow up,
I added a short section to the AD9154-FMC-EBZ User Guide on our wiki. Turns out FIN does need to be set when using the DACCLK PLL. It wasn't described very clearly in the original version. Please take a look here, in the Clock Input subsection:
Please let me know if you have any questions.
Hello landsman,Thank you for your support.I have a question about your mentioned User's Guide.In the Clock Input section, it looks like the AD9516 has "FIN pin.But AD9516 has not "FIN" pin.Is that a "CLK+/-" pin ?Best regards,y-suzuki