Hi,
is it possible to get an output update rate of 125 MSPS with the DAC family AD9763 AD9765 AD9767 in the Interleaved mode?
According to datasheet Rev G. the latch pulse width (t_LPW, t_CPW) must be at least 3.5 ns.
For the interleaved mode, a 250 MHz clock is required for a 125 MHz update rate on the IQWRT and IQCLK pin, which means that the high and low time can be only 2ns with a 50% duty cycle.
This raises the question of whether the 125 MSPS update rate can only be achieved in the dual-port mode or also in the interleaved mode.
Thank you
Michael
