tl;dr - Running the AD9106-EBZ with an input clock of 400 kHz causes the DACs to drift out of phase and intermittently drop out. Why?
We're attempting to use the AD9106 as a multichannel ramp generator, with a ramp frequency of 20-40 Hz. Currently testing with the AD9106-EBZ eval board.
We want to be able to control the amplitude of each ramp signal individually, so we can't use the build-in sawtooth.
Currently, we use 2000 steps into the SRAM for each DAC ramp.
In order to have a 40ms ramp with 1 step per CLK, we set the input clock to 50 kHz... (400kHz into the AD9106-EBZ).
When triggered, the ramps show up! But soon one of the signals will intermittently halt, or will drift out of phase. The only way to get them back is to re-trigger the signal.
When I run it with an input clock of 25 MHz (200 MHz into the AD9106-EBZ) (500x faster clock), everything works nominally, just a lot faster.
Why is this happening? I don't see any information on the datasheet about a lower-bound on clock frequency...
Is this an issue with the AD9514 clock divider that comes with the board? Is there also a limitation on the AD9106?
Thanks for your help...