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AD9106: CAL_CLK_DIV and BGDR bits


I am working with the AD9106 for a new product line. According to the datasheet, the BGDR adjusts the reference voltage value by means of six bits [5:0]. However, there is not a clear relation between the binary code and the final voltage value applied.

The same happens with the CAL_CLK_DIV bits. Here the clock divider value is setting by means of three bits [2:0], but the relation between the binary code and the final value applied is confuse. This remains confuse in the LabView software provided to work with the EVAL AD9106 board: here there are only four eligible values (CLK/32, CLK/64, CLK/128 and CLK/256), and none of them allow to accomplish with a frequency of calibration less than 500KHz if CLK=180MHz, which is a constrain given in the datasheet. 

Best regards,