AD9106: CAL_CLK_DIV and BGDR bits

Hi C.J.,

The BGDR code adjusts the reference voltage by adding/subtracting up to 20% of the nominal voltage output of the REFIO pin. The nominal voltage is approximately 1V and is referenced as BGDR = 0x00 (zero code). Since the BGDR code is in two's complement mode, the first half of the whole range of the 6bits (0 to 31 in decimal) adds up to 20% of the zero code value (0.625% of zero code for every bit increment). For the other half (32 to 63), it subtracts the zero code with the same values. Figure 37 of the datasheet makes visualization easier.

For the CAL_CLK_DIV bits, have you already tried to test the auto-calibration using the four options (CLK/32, CLK/64, CLK/128, and CLK/256)? I think there's a discrepancy in the options at the LABVIEW software since the default divider is 512 (based on Datasheet). Kindly update me on what happens when you choose one of the options while we're looking into it.

Regards,

Mark

Hi there,

Any feedback about the CAL_CLK_DIV bits issue?

Best,
C.J.

Hi C.J.

Sorry for the late response. 

The CAL_CLK_DIV is 3bit wide and therefore has 7 possible clock divider values, from 4 to 512. 0x0 corresponds to divide by 4, and every bit increment corresponds to an increase in the divider value by a factor of 2 (0x1 = divide by 8, and so on). Setting the CAL_CLK_DIV bit to 0x7 will do you fine as it results in a calibration clock of 351.6kHz with a DAC clock of 180MHz.

Since there are only 4 options in the LABVIEW software, just leave it unchanged since it's default value is 512.

Regards,

Mark

Hi Mark,

All clear. Thanks a lot.

Regards,
C.J.

Hi Mark,

All clear. Thanks a lot.

Regards,
C.J.