AD9174 Maximum Analog output frequency generation

Hi MuniPrasad,

The SFDR curves we have displayed are from the tests our engineering team conducted. Based on our results, the curves for generation for more than 4 GHz are consistent. Due to parasitic capacitances and inductances at the output, a constant 100 Ω termination impedance cannot be easily maintained across the full operating frequency range of the AD9174, which can be anywhere between dc and >6 GHz, depending on the application. The output impedance of each DAC can be determined through measurement. Generally, when matching the DAC output to a typical single-ended 50 Ω load, a 2:1 balun is recommended when operating below ~2 GHz. A 1:1 balun is recommended when operating above ~2 GHz, which also extends the 3 dB roll-off of the output beyond 4 GHz with proper PCB layout techniques. 

For proper filter layout and component selection, which results in optimal performance for most applications, refer to the documentation of the AD9174- FMC-EBZ evaluation board. you may however customize the filter to fit a specific application, according to the PFD frequency, reference clock phase noise, and DAC output phase noise requirements. For example, to lower DACCLK jitter when using the PLL, a higher PFD frequency minimizes the contribution of in band noise from the PLL. Set the PLL filter bandwidth such that the in band noise of the PLL intersects with the openloop noise of the VCO to minimize the contributions of both blocks to the overall noise.

Due to the current circumstances, the AD9174 eval tool is experiencing a slight delay as we look to resolve the issue soon. I hope this helps.

Best regards,

Zaid 

Hi,

Thanks for your detailed response. I am looking for single channel waveform generation, since AD9174 has 2 channel, we can split the entire frequency range as 20MHz to 2GHz for ch-1 and 2GHz to 6GHz for ch-2.

So the question now is with DAC sampling rate as 12.6GHz, will it be possible to generate waveform upto 6GHz. We are planning to have a external analog filter to filter out signals beyond 6GHz with rejection of 6.6GHz better than 50dB to eliminate the spur due to interpolation.

With this configuration is it possible to generate waveform from 20MHz to 6GHz (with 2 baluns). Are there any further limitations which need to be understood.

Also please do let us know whether the part can support DAC sampling clock of 12.6GHz, are there any limitations on JESD204 interface. The signal bandwidth is 80MHz (baseband) and interpolation rate of 64 is planned. With baseband datarate of 196.875MHz and 64x interpolation, is it possible to have DAC sampling rate of 12.6GHz and generate waveform upto 6GHz by programming the NCOs appropriately.

Hi MuniPrasad,

The AD9174 is capable of operating as a dual or single channel with update rates for the DAC up to 12.6 GSPS. In addition, the JESD204B interface supports rates up to 15.5 GSPS. Please refer to the table 13 in the data sheet for the JESD204B supported operating modes and interpolation combinations to appropriately select it for your application.However, the selectable interpolation filter for a complete set of input data rates are 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation and 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation. In addition, the AD9174 has a final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz

Best regards,

Zaid 

Whether AD9174 is pin compatible with AD9172, AD9173, AD9175 and AD9176. Can a common board layout be maintained to support all the chips.

Whether AD9174 is pin compatible with AD9172, AD9173, AD9175 and AD9176. Can a common board layout be maintained to support all the chips.

Yes