In the datasheet @ AD9963, about the clock doubler is following.
"CONFIGURING THE CLOCK DOUBLERS
The receive and transmit data paths each have a clock doubler used for clocking data through the device.
These clock doublers are only used in single data rate clocking mode, when there is no interpolation or decimation being used."
Is it corect ?
At the TX path, we look for following.
"The transmit path clock doubler is only used when all of the interpolation filters are bypassed (I = 1) and the transmit path is configured in bus rate mode (TX_SDR = 1)."
But at the RX path, we can not look for the comment about decimation filter.