Dear all,
we are having trouble setting up the DAC PLL of the AD1954 converter. We have an AC-coupled LVPECL clock at the CLK input pins and perform the following register writes according to the datasheet (e.g. for an input frequency of 500 MHz):
// DAC startup 0x000, 0xbd // soft reset 0x000, 0x3c // deassert reset, SPI 4-wire 0x011, 0x00 // power-up bandgap 0x080, 0x04 // power-up clocks (DCC) 0x081, 0x00 // power-up SYSREF 0x12d, 0x8b // fixed (digital dapath config) 0x146, 0x01 // fixed (digital dapath config) 0x333, 0x01 // fixed (JESD i/f config) // PLL 0x087, 0x62 // optimal settings (fixed) 0x088, 0xc9 0x089, 0x0e 0x08a, 0x12 0x08d, 0x7b 0x1b0, 0x00 0x1b5, 0xc9 0x1b9, 0x24 0x1bc, 0x0d 0x1be, 0x02 0x1bf, 0x8e 0x1c0, 0x2a 0x1c1, 0x2a 0x1c4, 0x7e 0x1c5, 0x06 0x08b, 0x02 // LODivMode 0x08c, 0x03 // RefDivMode 0x085, 0x08 // BCount 0x1b4, 0x60 // LookupVals 0x1b6, 0x49 0x1bb, 0x13 0x083, 0x10 // enable PLL
After a couple of milliseconds, we expect to see the PLL lock to a DACCLK of 1 GHz, but the status register 0x084 settles to 0xa0, i.e. CP_OVERRANGE_H and CP_CAL_VALID.
We have tried different combinations of reference frequency, f_DACCLK and divider values, to no avail. Triggering a recalibration does not help either. Reading back the configuration registers gives the right values.
As the PLL configuration basically consists of only three dividers, we are running out of ideas of what to try next. Any advice is greatly appreciated.
Thank you and best regards
David
