Hi sir/madam ,
I am using FMCDAQ3 with ZC706 . Initially I am trying to use DAC(AD9152) . For this I downloaded the FPGA reference design and modifed the SDK code as per the "EXAMPLE START-UP SEQUENCE" from AD9152 data sheet .
When I followed the "EXAMPLE START-UP SEQUENCE" then I am not getting any output and the UART prints are as follows
AD9152: CGS NOT received
AD9152: ILAS NOT received
AD9152: framer OUT OF SYNC
AD9152: check - sum MISMATCH
please help me to solve this .
THANKS AND REGARDS
Did you first try the code that came with the reference design before modifying the SDK? If using the example script in the DS, you must also configure the FPGA with the appropriate JESD204B parameters and clock input. You should also verify that the JESD configuration is supported by the FPGA reference design (supported modes are listed in the user guide). I am also copying CsomI in case he has further comments fromthe FPGA reference design side of things.
I configured the JESD204B parameters correctly and the DAC is working. But I am facing some problem regarding interpolation which I stated in the below thread
Thanks and Regards