Questions about inner block performance and DAC core feasibility of AD9162

Hello,

My customer are considering to use AD9162 at their RADAR platform.

For this, they are reviewing the performance of AD9162 including inner block operation and performance per inner blocks.

Below diagrams are a RF UP converter part with AD9162 which they will want to implement and a inner blaock of AD9162 (NCO & DAC core).

Please refer below questions an dlet me know your answers.

Q1.) When input data rate of AD9162 is 1.5GSPS, what is values of data rate at digital filters and NCO output?

1-1)Output of first 2x HB? (Is this 3GSPS?)

1-2 2)Output of second 2x HB? (Is this GSPS or 12GSPS? )

Q2. what is the operating sampling rate of NCO and DSP core at activated 2NRZ HB filter?

       (Are the same value 12GSPS?)

Q3. which clock of ±CLK signal is needed for supporting 12GSPS of DAC core output data rate? (Is this 6GHz?)

Q4. As the datasheet (69 page) of AD9126, NCO modulator has two output signals OUT_I & OUT_Q.

       But in case of AD9162, it has one DAC core.

       4-1) How to select OUT_I and OUT_Q at DAC core input among two output signals of NCO modulator?

       4-2) Can they select OUT_I signal only for DAC core input?

Regards,

Se-woong

PS. Attached file has

same questions.

Parents
  • +1
    •  Analog Employees 
    on Jan 28, 2020 10:50 PM

    Q1.) When input data rate of AD9162 is 1.5GSPS, what is values of data rate at digital filters and NCO output?

    1-1)Output of first 2x HB? (Is this 3GSPS?)

    • Yes, the output of the first 2xHB filters will be 3GSPS.

    1-2 2)Output of second 2x HB? (Is this GSPS or 12GSPS? )

    • The output of the second 2x HB filters will be 6GSPS. For 12Gsps, it will need one extra 2x HB.

    Q2. what is the operating sampling rate of NCO and DSP core at activated 2NRZ HB filter?   (Are the same value 12GSPS?)

    • The final half-band filter, FIR85, is used in the 2× NRZ mode. It is clocked at the 2 × FCLK(=fDAC) rate. NCO clocking rate is same with DAC rate. i.e. if DAC rate is 12Gsps, NCO rate is at 12GHz and FIR85 filter is also at 12GHz.

    Q3. which clock of ±CLK signal is needed for supporting 12GSPS of DAC core output data rate? (Is this 6GHz?)

    • An Input clock rate of 6 GHz is needed to generate the 12GSPS for fDAC when FIR85 enabled and DAC is in DDR mode.

     

     

    Q4. As the datasheet (69 page) of AD9126, NCO modulator has two output signals OUT_I & OUT_Q.       But in case of AD9162, it has one DAC core.

           4-1) How to select OUT_I and OUT_Q at DAC core input among two output signals of NCO modulator?

           4-2) Can they select OUT_I signal only for DAC core input?

    • For Q4, the DAC has one core and therefore you can only get the OUT_I data. The OUT_Q is dropped off. So, it’s not programmable to select I data or Q data.
Reply
  • +1
    •  Analog Employees 
    on Jan 28, 2020 10:50 PM

    Q1.) When input data rate of AD9162 is 1.5GSPS, what is values of data rate at digital filters and NCO output?

    1-1)Output of first 2x HB? (Is this 3GSPS?)

    • Yes, the output of the first 2xHB filters will be 3GSPS.

    1-2 2)Output of second 2x HB? (Is this GSPS or 12GSPS? )

    • The output of the second 2x HB filters will be 6GSPS. For 12Gsps, it will need one extra 2x HB.

    Q2. what is the operating sampling rate of NCO and DSP core at activated 2NRZ HB filter?   (Are the same value 12GSPS?)

    • The final half-band filter, FIR85, is used in the 2× NRZ mode. It is clocked at the 2 × FCLK(=fDAC) rate. NCO clocking rate is same with DAC rate. i.e. if DAC rate is 12Gsps, NCO rate is at 12GHz and FIR85 filter is also at 12GHz.

    Q3. which clock of ±CLK signal is needed for supporting 12GSPS of DAC core output data rate? (Is this 6GHz?)

    • An Input clock rate of 6 GHz is needed to generate the 12GSPS for fDAC when FIR85 enabled and DAC is in DDR mode.

     

     

    Q4. As the datasheet (69 page) of AD9126, NCO modulator has two output signals OUT_I & OUT_Q.       But in case of AD9162, it has one DAC core.

           4-1) How to select OUT_I and OUT_Q at DAC core input among two output signals of NCO modulator?

           4-2) Can they select OUT_I signal only for DAC core input?

    • For Q4, the DAC has one core and therefore you can only get the OUT_I data. The OUT_Q is dropped off. So, it’s not programmable to select I data or Q data.
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