we are currently working with the AD9142A in following setup:
- data input and control from Intel Cyclone V
- output via ADL5375 Quadratur Modulator
Operation mode is set as follows:
- 8x interpolation
- external clks only (900 MHz DACCLK, 112.5 MHz DCI)
- word interface mode (16 bit)
- delay line interface mode (112.5 MHz < min. 250 MHz for DLL)
- fifo depth 4 ints (default)
When activating SED/AED control in register 60 the output signal either improves (less spectral sidelobes) or is completely deactivated. So far it seems unpredictable, why this is happening.
Furthermore the SED fails frequently when applying strong bit toggling, but passes, when applying CW - constant digital data - to the input ports. I tried to check for errors in the FPGA code, but the recorded output data seems to be fine. Both the frame signal and DCI are using the same pin setup like the data LVDS pins. Additionally all possible delay line taps and a DCI phase shift in the FPGA were tested, to account for unlikely data transitions in the data-read window.
Is it possible to use SED with delay line interface? I'm wondering, because in the functional block diagramm the SED block is connected to DLL. Plus the datasheet mentions the delay line mode after the SED chapter.
We are somewhat confused, since the datasheet gives no more information. Your help is highly appreciated! Thanks a lot.
Kind regards hansi