AD9142A - SED/AED function affecting output

Good evening,

we are currently working with the AD9142A in following setup:

  • data input and control from Intel Cyclone V
  • output via ADL5375 Quadratur Modulator

Operation mode is set as follows:

  • 8x interpolation
  • external clks only (900 MHz DACCLK, 112.5 MHz DCI)
  • word interface mode (16 bit)
  • delay line interface mode (112.5 MHz < min. 250 MHz for DLL)
  • fifo depth 4 ints (default)

When activating SED/AED control in register 60 the output signal either improves (less spectral sidelobes) or is completely deactivated. So far it seems unpredictable, why this is happening.

Furthermore the SED fails frequently when applying strong bit toggling, but passes, when applying CW - constant digital data - to the input ports. I tried to check for errors in the FPGA code, but the recorded output data seems to be fine. Both the frame signal and DCI are using the same pin setup like the data LVDS pins. Additionally all possible delay line taps and a DCI phase shift in the FPGA were tested, to account for unlikely data transitions in the data-read window.

Is it possible to use SED with delay line interface? I'm wondering, because in the functional block diagramm the SED block is connected to DLL. Plus the datasheet mentions the delay line mode after the SED chapter.

We are somewhat confused, since the datasheet gives no more information. Your help is highly appreciated! Thanks a lot.

Kind regards hansi

Parents
  • We finally found the answer ourselves:

    In 4 word SED mode, one has to provide alternating I_0, Q_0, I_1, Q_1, I_0, Q_0, I_1, Q_1, ... words. Any single I_0, Q_0 or every I_0, Q_0 sample may be accompanied by a frame signal to indicate the first input samples.

    It is not possible to feed a bunch of words (e.g. a full repetitive digital stream, consisting of 200 words) and compare only two consecutive words by giving the specific frame signal. The SED will always repeat after each two DCI cycles.

    Given the above, there is no point in having a proper DAC output while using the SED/AED function. We will disable TX while using the SED circuitry.

    Thanks for you efforts.

  • +1
    •  Analog Employees 
    on Feb 20, 2020 6:33 PM 9 months ago in reply to hansi

    Yes you are correct, I think I didn't realize what you were trying to do. The SED functionality is purely meant to be used as a test or characterization feature - not a functioning mode for regular transmission. At most you can only have 4 unique individual words in your pattern (they don't necessarily have to be I/Q data). This is done because you have to program the expected values into the registers of the part (Registers 0x68 - 0x6F) so you can not program a long pattern. In the datasheet in the SED Example section it explains the steps needed to set up the part for the compare. This is generally used to do testing so if it's desired the data clock can be swept and time delayed externally to see where the best timing edge location would be for a customer's actual system board to accommodate for any potential skew in the data line routing on the PCB. Then once that timing is determined it can be fixed and normal transmission operation is used. This is not a 'real time' sample error detection feature.

Reply
  • +1
    •  Analog Employees 
    on Feb 20, 2020 6:33 PM 9 months ago in reply to hansi

    Yes you are correct, I think I didn't realize what you were trying to do. The SED functionality is purely meant to be used as a test or characterization feature - not a functioning mode for regular transmission. At most you can only have 4 unique individual words in your pattern (they don't necessarily have to be I/Q data). This is done because you have to program the expected values into the registers of the part (Registers 0x68 - 0x6F) so you can not program a long pattern. In the datasheet in the SED Example section it explains the steps needed to set up the part for the compare. This is generally used to do testing so if it's desired the data clock can be swept and time delayed externally to see where the best timing edge location would be for a customer's actual system board to accommodate for any potential skew in the data line routing on the PCB. Then once that timing is determined it can be fixed and normal transmission operation is used. This is not a 'real time' sample error detection feature.

Children
No Data