I am developing FPGA design (not using analog devices data generation boards) to transmit data to AD9172 eval board using JESD204B protocol. The JESD204B is supposed to work in mode 3, subclass 1 with SYSREF enabled. I want to leave the configuration of HMC7044 and AD9172 to ACE for now, so that all SPI configuration goes through USB. Setup is the following:
Input data rate: 491.52 MHzJESD mode: 3Channel interp: 3Datapath interp: 8
However, when I measure the frequency of SYSREF clock on the board, it is not 15.36MHz, as it says in ACE but approximately half of it. Also, the reference clock (BR40_P/N) is not coming from the board (but it should be 245.76 MHz). Could it be an issue with ACE?
It's a bit weird. if the HMC7044 is configured correctly, all the clocks will be generated correctly. but If SYSREF freq is exact half of 15.36MHz, it should not impact the subclass1 operation. The SYSREF should be integer multiple of LMFC cycles. LMFC calculation can be found in the datasheet.