AD9176 Multichip Sync: internal PLL best practice?

We are architecting a custom system with 2 or 4 AD9176, with sample rates of 6, 8, or 10 Gsps.  The outputs are required to be synchronized.

What is best practice concerning device clocking?

A) Generate sample clock ( 6, 8, 10 GHz) and SYSREF externally

B) Generate REF clock (~125 MHz) and SYSREF externally, then use internal PLLs to generate sample clock?

I appreciate your comments.c

  • +1
    •  Analog Employees 
    on Feb 4, 2020 10:20 PM 11 months ago

    Dear cpike, 

    In a multi DAC system, the design looks for optimum deterministic latency operation , consider the timing distribution skew of the SYSREF± signal. Theoretically, the better approach is option A, resulting in a better Deterministic Latency (DL) by a single DACCLK cycle. But this comes at the expense of more complex PCB design, routing GHz clock rates. option B will have slightly worse DL, since the two devices, post SYREF sync, could have a relative phase offset of 1 DACCLK cycles max. So both options work, but the PCB design of option A would increase the complexity of externally clocking considerably, with only slight improvement to DL.