AD9176 Multichip Sync: internal PLL best practice?

We are architecting a custom system with 2 or 4 AD9176, with sample rates of 6, 8, or 10 Gsps.  The outputs are required to be synchronized.

What is best practice concerning device clocking?

A) Generate sample clock ( 6, 8, 10 GHz) and SYSREF externally

B) Generate REF clock (~125 MHz) and SYSREF externally, then use internal PLLs to generate sample clock?

I appreciate your comments.c