We are evaluating the behavior of the AD9102 using the EVM.
What we are observing is that after each pattern period is executed, the DAC output goes to midrange.
Is there a way to prevent this?
We are storing a waveform in SRAM and we are executing a single pattern period. We would like the output to stay and hold the last value in the pattern. (the value written in SRAM at address STOP_ADDR).
Can we please get an answer to this?
We are in the last stage of the design and the behavior I outlined earlier is a show stopper for our application requirements.
Assumed answered offline. Please let us know if we need to keep this case open.