I am FAE in Japanease distributor.
Our customer uses two AD9739 at synchronous mode with DACCLK=1GHz, DCI=250MHz and SCLK=17MHz.
They intializes two AD9739 based on table32 of Datasheet.
But the initilazation does not work correctly.
Could you inform how to fix the phenomeno by 10th on December?
Attaced Connection.pdf shows the customer's hardware connection.
Attaced Waveform.pdf shows the intializaation steps and waveform pictures.
Waveform.pdf shows the putput waveforms of DAC1(master) and DAC2(slave) are corrct after step9.
But the waveform of DAC1(master) is not correct and the waveform of DAC2(slave) is correct after step26.
At step 28, Register 0x21 value is 0x99.
Our customer confimed the waveforms worked correctly before step26.
Regsiter(0x1B) of master was confimed CD and Register(0x1C) of master was confimed 3B at first time step29.
Register(0x1B) of slave was confimed 40 and Register(0x1C) of slave was confimed 3C at first time step29.
That meant DCL_DEL of master was 0x0EF and it of slave was 0x0F1 at first time step29.
DCL_DEL of master was 0x0EE and it of slave was 0x0F0 at 2nd time step29.
DCL_DEL of master was 0x0ED and it of slave was 0x0F2 at 3rd time step29.
Thank you in advance.
Thank you for reply.
Our customer use two AD9739 syn controller enabled.
You recomend CLKDIVPH phase rotation.
But page 38 of Datasheet Rev.E mentions ''It is not possible to manually rotate the divide-by-4 phases of the data path with the syn controller enabled."
Should our custemer try CLKDIVPH phase rotation with the syn controller enabled?
In that case, they will need to double their data rate to avoid performing the clock rotation.