Urgent question AD9739 initialization issue

I am FAE in Japanease distributor.

Our customer uses two AD9739 at synchronous mode with DACCLK=1GHz, DCI=250MHz and SCLK=17MHz.

They intializes two AD9739 based on table32 of Datasheet.

But the initilazation does not work correctly.

Could you inform how to fix the phenomeno by 10th on December?

Attaced Connection.pdf shows the customer's hardware connection.

Attaced Waveform.pdf shows the intializaation steps and waveform pictures.

Waveform.pdf shows the putput waveforms of DAC1(master) and DAC2(slave) are corrct after step9.

But the waveform of DAC1(master) is not correct and the waveform of DAC2(slave) is correct after step26.

At step 28, Register 0x21 value is 0x99.

Our customer confimed the waveforms worked correctly before step26.

Regsiter(0x1B) of master was confimed CD and Register(0x1C) of master was confimed 3B at first time step29.

Register(0x1B) of slave was confimed 40 and Register(0x1C) of slave was confimed 3C at first time step29.

That meant DCL_DEL of master was 0x0EF and it of slave was 0x0F1 at first time step29.

DCL_DEL of master was 0x0EE and it of slave was 0x0F0 at 2nd time step29.

DCL_DEL of master was 0x0ED and it of slave was 0x0F2 at 3rd time step29.

Thank you in advance.

N.Kokubo

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  • Hello

      I asked our customer question 9th on December.

    Could you answer it?

    Who can ansewer?

    I am FAE in Japanease distributor.

    Our customer uses two AD9739 at synchronous mode with DACCLK=1GHz, DCI=250MHz and SCLK=17MHz.

    They intializes two AD9739 based on table32 of Datasheet.

    But the initilazation does not work correctly.

    Could you inform how to fix the phenomeno by 10th on December?

    Attaced Connection.pdf shows the customer's hardware connection.

    Attaced Waveform.pdf shows the intializaation steps and waveform pictures.

    Waveform.pdf shows the putput waveforms of DAC1(master) and DAC2(slave) are corrct after step9.

    But the waveform of DAC1(master) is not correct and the waveform of DAC2(slave) is correct after step26.

    At step 28, Register 0x21 value is 0x99.

    Our customer confimed the waveforms worked correctly before step26.

    Regsiter(0x1B) of master was confimed CD and Register(0x1C) of master was confimed 3B at first time step29.

    Register(0x1B) of slave was confimed 40 and Register(0x1C) of slave was confimed 3C at first time step29.

    That meant DCL_DEL of master was 0x0EF and it of slave was 0x0F1 at first time step29.

    DCL_DEL of master was 0x0EE and it of slave was 0x0F0 at 2nd time step29.

    DCL_DEL of master was 0x0ED and it of slave was 0x0F2 at 3rd time step29.

    Thank you in advance.

    N.Kokubo

  • Hello

      I asked our customer question 9th on December.

    Could you answer it?

    Who can ansewer?

    I am FAE in Japanease distributor.

    Our customer uses two AD9739 at synchronous mode with DACCLK=1GHz, DCI=250MHz and SCLK=17MHz.

    They intializes two AD9739 based on table32 of Datasheet.

    But the initilazation does not work correctly.

    Could you inform how to fix the phenomeno by 10th on December?

    Attaced Connection.pdf shows the customer's hardware connection.

    Attaced Waveform.pdf shows the intializaation steps and waveform pictures.

    Waveform.pdf shows the putput waveforms of DAC1(master) and DAC2(slave) are corrct after step9.

    But the waveform of DAC1(master) is not correct and the waveform of DAC2(slave) is correct after step26.

    At step 28, Register 0x21 value is 0x99.

    Our customer confimed the waveforms worked correctly before step26.

    Regsiter(0x1B) of master was confimed CD and Register(0x1C) of master was confimed 3B at first time step29.

    Register(0x1B) of slave was confimed 40 and Register(0x1C) of slave was confimed 3C at first time step29.

    That meant DCL_DEL of master was 0x0EF and it of slave was 0x0F1 at first time step29.

    DCL_DEL of master was 0x0EE and it of slave was 0x0F0 at 2nd time step29.

    DCL_DEL of master was 0x0ED and it of slave was 0x0F2 at 3rd time step29.

    Thank you in advance.

    N.Kokubo

Reply
  • Hello

      I asked our customer question 9th on December.

    Could you answer it?

    Who can ansewer?

    I am FAE in Japanease distributor.

    Our customer uses two AD9739 at synchronous mode with DACCLK=1GHz, DCI=250MHz and SCLK=17MHz.

    They intializes two AD9739 based on table32 of Datasheet.

    But the initilazation does not work correctly.

    Could you inform how to fix the phenomeno by 10th on December?

    Attaced Connection.pdf shows the customer's hardware connection.

    Attaced Waveform.pdf shows the intializaation steps and waveform pictures.

    Waveform.pdf shows the putput waveforms of DAC1(master) and DAC2(slave) are corrct after step9.

    But the waveform of DAC1(master) is not correct and the waveform of DAC2(slave) is correct after step26.

    At step 28, Register 0x21 value is 0x99.

    Our customer confimed the waveforms worked correctly before step26.

    Regsiter(0x1B) of master was confimed CD and Register(0x1C) of master was confimed 3B at first time step29.

    Register(0x1B) of slave was confimed 40 and Register(0x1C) of slave was confimed 3C at first time step29.

    That meant DCL_DEL of master was 0x0EF and it of slave was 0x0F1 at first time step29.

    DCL_DEL of master was 0x0EE and it of slave was 0x0F0 at 2nd time step29.

    DCL_DEL of master was 0x0ED and it of slave was 0x0F2 at 3rd time step29.

    Thank you in advance.

    N.Kokubo

Children
  • Hello

      I am FAE in Japanease distributor.

      I asked our customer question 9th on December.

    Could you answer it ? Who can supoourt us ?

    Our customer uses two AD9739 at synchronous mode with DACCLK=1GHz, DCI=250MHz and SCLK=17MHz.

    They intializes two AD9739 based on table32 of Datasheet.

    But the initilazation does not work correctly.

    Could you inform how to fix the phenomeno by 10th on December?

    Attaced Connection.pdf shows the customer's hardware connection.

    Attaced Waveform.pdf shows the intializaation steps and waveform pictures.

    Waveform.pdf shows the putput waveforms of DAC1(master) and DAC2(slave) are corrct after step9.

    But the waveform of DAC1(master) is not correct and the waveform of DAC2(slave) is correct after step26.

    At step 28, Register 0x21 value is 0x99.

    Our customer confimed the waveforms worked correctly before step26.

    Regsiter(0x1B) of master was confimed CD and Register(0x1C) of master was confimed 3B at first time step29.

    Register(0x1B) of slave was confimed 40 and Register(0x1C) of slave was confimed 3C at first time step29.

    That meant DCL_DEL of master was 0x0EF and it of slave was 0x0F1 at first time step29.

    DCL_DEL of master was 0x0EE and it of slave was 0x0F0 at 2nd time step29.

    DCL_DEL of master was 0x0ED and it of slave was 0x0F2 at 3rd time step29.

    Best regards

    N.Kokubo

  •  I am FAE in Japanease distributor.

      I asked our customer question 9th on December.

    Could you suggest following question?

    Our customer uses two AD9739 at synchronous mode with DACCLK=1GHz, DCI=250MHz and SCLK=17MHz.

    They intializes two AD9739 based on table32 of Datasheet.

    But the initilazation does not work correctly.

    Could you inform how to fix the phenomeno by 10th on December?

    Attaced Connection.pdf shows the customer's hardware connection.

    Attaced Waveform.pdf shows the intializaation steps and waveform pictures.

    Waveform.pdf shows the putput waveforms of DAC1(master) and DAC2(slave) are corrct after step9.

    But the waveform of DAC1(master) is not correct and the waveform of DAC2(slave) is correct after step26.

    At step 28, Register 0x21 value is 0x99.

    Our customer confimed the waveforms worked correctly before step26.

    Regsiter(0x1B) of master was confimed CD and Register(0x1C) of master was confimed 3B at first time step29.

    Register(0x1B) of slave was confimed 40 and Register(0x1C) of slave was confimed 3C at first time step29.

    That meant DCL_DEL of master was 0x0EF and it of slave was 0x0F1 at first time step29.

    DCL_DEL of master was 0x0EE and it of slave was 0x0F0 at 2nd time step29.

    DCL_DEL of master was 0x0ED and it of slave was 0x0F2 at 3rd time step29.

    Best regards

    N.Kokubo

  • 0
    •  Analog Employees 
    on Feb 19, 2020 11:00 PM 9 months ago in reply to NKokubo131

    So sorry for the delay!  The minimum DAC rate of the AD9739 is actually 1.6Gsps.  However, the latest revision of the data sheet (revE) describes how the AD9739 can be operated at rates below this in the "Data Receiver Operation at Lower Clock Rates" section (pg 32).  I have pasted inthat section here for your convenience:

    Data Receiver Operation at Lower Clock Rates
    At clock rates below 1.6 GSPS, it is recommended to include provisions to rotate the CLKDIVPH setting in the SPI boot process. As previously mentioned, the delay line can be varied over a nominal 4 ns window. If the minimum specified clock rate of 800 MSPS is considered, a DCI clock rate of 200 MSPS corresponds to a 5 ns period, thus exceeding the delay line length. Therefore, it becomes possible that the initial startup phase from the divide-by-4 circuit (and DCO output) is such that the data receiver controller can never establish initial lock upon power up.

        If the clock rate is increased to 1600 MSPS (that is, DCI clock period of 2.5 ns), the controller always finds at least two DCI clock edges, therefore, establishing lock. However, should the DCI edges fall symmetrically (equal distance) from the initial DCI_DEL midscale setting, a guard band of ±0.75 ns (that is, (4.0 − 2.5)/2) results. Rotating the CLKDIVPH can result in an improvement in this case by skewing one of the DCI edges toward the DCI_DEL midscale value.

        Rotating the CLKDIVPH phase provides a means of adjusting the delay in course steps of fDAC/4. For example, in the 800 MSPS and 1600 MSPS cases described above, rotating the CLKDIVPH setting by 1 corresponds to a delay shift of 5 ns and 2.5 ns, respectively. By adding an additional step in the SPI initialization routine for the data receiver controller, it becomes possible to increase the effective range of the delay line to ensure a DCI_DEL value that falls within a reasonable guard band.

        In some situations, rotating the phase alone may not be sufficient to create the conditions necessary for the data receiver to lock. This is likely due to a particular misalignment of clock edges within the device that can occur after power up or reset at clock rates below 1.6 GHz. In these situations, it is necessary to
    power down the device by taking the following steps:

    1. Set the four power-down bits in Register 0x01 (Register 0x01 = 0x33).

    2. Reset the power-down bits to 0 (Register 0x01 = 0x00)

    3. Follow the start-up sequence, including possible phase rotation, as described previously.

    4. These three steps may need to be initiated multiple times to achieve a successful lock.

  • Hello

    Thank you for reply.

    Our customer use two AD9739 syn controller enabled.

    You recomend CLKDIVPH phase rotation.

    But page 38 of Datasheet Rev.E mentions ''It is not possible to manually rotate the divide-by-4 phases of the data path with the syn controller enabled."

    Should our custemer try CLKDIVPH phase rotation with the syn controller enabled?

    Best regards

    N.Kokubo

  • 0
    •  Analog Employees 
    on Feb 21, 2020 4:32 PM 9 months ago in reply to NKokubo131

    In that case, they will need to double their data rate to avoid performing the clock rotation.