In the schematic of EVAL-AD916X board provided in the link(https://www.analog.com/media/en/technical-documentation/eval-board-schematic/AD916(2_4)-FMC(122)-EBZ%20RevC%20Schematic.pdf), I found some positive nets are connected to the negetive pins of FMC conntector and some negetive nets are connected to the positive pins of FMC conntector.
For example in sheet 8, SERDIN7_N is conntected to DP5_C2M_P of the FMC connector, and SERDIN7_P is conntected to DP5_C2M_N. Below is the picture that shows the error:
So I suspect whether the FPGA can communicate with the AD9162 correctly.
For signal routing, it may be useful to change the lane order or "flip" the polarity of specific lanes, Both the AD9162 (reg 0x334) and the FPGA have the ability to do both of these things so PCB routing is made easier.