I’m reaching out to you again since I have not received any support from my last email. I’m trying to interface your AD9176 evaluation board to an Intel Stratix 10 FPGA evaluation board and the DAC just doesn’t seem to be responding. I can’t get anything to come out of the DAC. The link on the Stratix side shows everything is fine. It’s gone through all of the initialization phases and it’s in user mode sending data to the DAC. However, the DAC shows that it hasn’t finished the first phase of link initialization…CGS. I’m observing the link status of the DAC on the ACE front panel, as seen in the pic below, as well as reading the memory mapped registers. I’ve tried multiple configurations from 8 lanes to 4 to 1 lane. I’m using on-board clocking with everything set to multiples of the 122.88Mhz reference. I’ve inverted the 0-3 lanes as per the eval board schematic. I’ve tried clocking the FPGA link with the DAC gtx output clock as well as internal Startix eval clocks. Nothing is working.
I simply need to know what electrical connections to make to interface properly to your AD9176 eval card and what clocking and configuration do I need? What’s the setup? What’s the process to get it through the initialization phase?
sorry for the late response.
i didn't see the pic what you mentioned. can you repost it?
the lane polarity should not impact the first step CGS. it seems the FPGA clock isn't synced with the board clock. is your FPGA serdes REF CLK from AD9176 evaluation board? It's supposed to lane rate/40 per our design.
can you see a tone out of DAC in NCO test mode?
I've tried using the REF CLK from the AD9176. Also tried using the REF CLK from the FPGA board. I get the same result...nothing out of the DAC and no confirmation that CGS initialization has completed.
It seems to me the DAC was programmed correctly. can you post your ACE board/part configuration screenshots? As asked earlier, can you see a tone out of DAC in NCO/DC test mode without FPGA SERDES?