1. We are able to configure the PLL AD9516 to generate required clocks for DAC AD9125 chip( REF CLK, DAC CLK).2. Digital data along with clock is given through FPGA.3.DAC is configured through SPI using register configuration given in ACE GUI software.
DACCLK input = 400 MHz (from AD9516 PLL)REFCLK = 100MHZ (from AD9516 PLL)DCI = 200 MHz ( from FPGA)data input = 20MHz at 200msps ( from FPGA)
Can you provide the DAC configuration register values for this clock settings
Are you using the on-chip PLL for the AD9125? You only need to provide either a DAC Clock OR a Reference clock (if you're using the on-chip PLL).
Could you send a screenshot of how you are setting up the ACE GUI and DPGDownloader?