AD9162 BER Test Using ADS7

Hi,

I'd like to run a BER Test using the AD9162 evaluation board.

Can the ADS7 transmiiter be commanded to output a PRBS?

Thanks

-Brian



tagged
[edited by: JValeriani at 5:29 PM (GMT 0) on 11 Oct 2019]
Parents
  • +1
    •  Analog Employees 
    on Oct 11, 2019 5:21 PM

    The ADS7 (V1, V2) and the ADS8 DO support PRBS7, `15, `23, and ’31 modes (I’ve used them in loopback tests). These modes are accessible through (FPGA) register 0x3a0. The (mentioned) registers ARE directly accessible through Python.

     

    One common area of confusion…

    The above modes COMPLETELY bypass JESD204 mode(s) and send raw PRBS data across the link(s). This is NOT 8b10b encoded.

    I’ve seen some cases where the PRBS is sent through the JESD mode (encoding the PRBS data across the link).

     

    Assuming you are running the first method (PRBS directly on the link), you must first set up the Link (polarity, rate, etc.) and then turn on the PRBS mode.

    Then, put the receiver (i.e. DAC) into (the equivalent) PRBS mode (expect NO feedback such as SYNC, etc. within the FPGA). All further verification (i.e. resetting and then measuring BER) is done within the DAC.

Reply
  • +1
    •  Analog Employees 
    on Oct 11, 2019 5:21 PM

    The ADS7 (V1, V2) and the ADS8 DO support PRBS7, `15, `23, and ’31 modes (I’ve used them in loopback tests). These modes are accessible through (FPGA) register 0x3a0. The (mentioned) registers ARE directly accessible through Python.

     

    One common area of confusion…

    The above modes COMPLETELY bypass JESD204 mode(s) and send raw PRBS data across the link(s). This is NOT 8b10b encoded.

    I’ve seen some cases where the PRBS is sent through the JESD mode (encoding the PRBS data across the link).

     

    Assuming you are running the first method (PRBS directly on the link), you must first set up the Link (polarity, rate, etc.) and then turn on the PRBS mode.

    Then, put the receiver (i.e. DAC) into (the equivalent) PRBS mode (expect NO feedback such as SYNC, etc. within the FPGA). All further verification (i.e. resetting and then measuring BER) is done within the DAC.

Children
No Data