AD9144 JESD issue

Hi,

I am having trouble with JESD link while using ZC706 along with AD9144.

I have set up JESD inside FPGA which is configured as below:

scrambling:off

F=2, K=32, Subclass =0, line rate =4.32 Gbps,ref clock = 108MHz , M= 4, N and Np =16 and S =1

I have set up the DAC as mentioned in datasheet for mode 2.

when i monitored 0x084 and 0x 281 it shows pll and serdes pll locked.

But am not getting sync high status from DAC and JESD at transmit side inside FPGA continues to send K.25 characters.

When i tried to read fifo status, it shows some values in fifo always (either fifo full or fifo empty).

Where am doing mistake. If its clock issue then why pll is locked.

Pl help further.

Thanks



tagged
[edited by: JValeriani at 7:51 PM (GMT 0) on 10 Oct 2019]
  • Also I would like to add the fifo error is gone. when i run prbs test it is also passed but some how sync is not up.Also when i tried to read 0x470 it never goes high.

    Means its not receiving comma characters. I checked all my pins connections and i have also taken care of lane inversion.

    Pl help.

    Thanks

  • +1
    •  Analog Employees 
    on Oct 10, 2019 4:03 PM in reply to shurde300

    Hello, >90% of all issues of not passing the CGS portion of the JESD204B sync process is due to clocking issues - either wrong frequency (the reference clocks need to be exact, not off by 10's of Hz or more) on one side of the link or bad signal  levels or signal integrity issues.  This would not necessarily preclude the PLL's on either end from locking since they lock to the reference provided, not any clocking frequency components sent over the link.  See this link for more debug guidance.