I am having trouble with JESD link while using ZC706 along with AD9144.
I have set up JESD inside FPGA which is configured as below:
F=2, K=32, Subclass =0, line rate =4.32 Gbps,ref clock = 108MHz , M= 4, N and Np =16 and S =1
I have set up the DAC as mentioned in datasheet for mode 2.
when i monitored 0x084 and 0x 281 it shows pll and serdes pll locked.
But am not getting sync high status from DAC and JESD at transmit side inside FPGA continues to send K.25 characters.
When i tried to read fifo status, it shows some values in fifo always (either fifo full or fifo empty).
Where am doing mistake. If its clock issue then why pll is locked.
Pl help further.
[edited by: JValeriani at 7:51 PM (GMT 0) on 10 Oct 2019]