AD9102/AD9106 delay between Trigger and Start of Generation from RAM

Question

Hi, 
 I use evaluation board and try to generate signal from RAM using TRIGGER pin. But I observe 500 us delay between TRIGGER (pin 32 "1"->"0") and start of generation from RAM while datasheet say that the typical delay should be 96 ns. 
 Configuration for DAC1 you can see below. 
 
 As you can see all delays are zeroes. But the real delay is 524 us. 
 
 How could I get 96 ns delay between Trigger and RAM generated signal? 
 
 Best regards, Ivan

deljones · Accepted Answer

Also, check this EZone case: https://ez.analog.com/data_converters/high-speed_dacs/f/q-a/22935/ad9102-help-with-trigger-programming/90506#90506 
 It looks like the min delay comes if you set the delay register to 0x0E (not 0x00). Delay is also affected by dac clk rate as implied above.)

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AD9102/AD9106 delay between Trigger and Start of Generation from RAM