I'm trying to connect AD9154 to FPGA JESD204 TX IP using AD9154-FMC-EBZ board and Xilinx ZC706 FPGA.
AD9154 is configured with ACE software.The Initial Configuration Summary is
Fdac= 1GHz, 4× interpolation, JESD204 Lane Rate = 5Gbps, Fref=125MHz,1M1L
FPGA JESD204 PHY configuration is
JESD204 PHY TX lane rate also set to 5G and the ref clock is supplied by GBTCLK0_M2C form AD9154-FMC-EBZ，125MHz. TX_RESET_DONE singal of the JESD204 PHY IP is high.
My JESD204 PHY TX is always sending K28.5 to AD9154,but the SYNCOUT0 signal stays low.
To my understand,the SYNCOUT0 signal should be high,and then CGS, then ILAS phase goes.
I'm a new player of JESD204 interface. Did I do something wrong, or there are any mistakes in my understanding?
I've found my mistake. Order of Lane 0~8 of AD9154 on AD9154-FMC-EBZ is inversed then connected to FMC.