I wanted to confirm how we are packing bits onto the JESD204B bus with the AD9176.
We are in Mode 4. We have a complex waveform we are sending to the DAC from our FPGA board. Currently we have lanes 0 - 3. In the table on page 34 the following is called out. it says for lane 0, Frame 0 has octet 0 and octet 1 as M0S0[15:8] and M0S0[7:0], respectively. Frame 1 would have M0S1[15:8] and M0S1[7:0]. Lane 1 would then have the M1Sx samples, etc. We've read that M in our case is for complex sub channels. So would it be correct to say that for us, the DAC 0 IQ data would go as follows:
M0Sx = DAC0 I Data for both channels, if so is S0 channel 0 and S1 channel 1?
M1Sx = DAC0 Q Data for both channel
Or is it:
M0S0 = DAC0 I data for channel 0, M0S1 is DAC0 Q data for Channel 0M1S0 = DAC0 I data for channel 1, M1S1 is DAC0 Q data for Channel 1
M0 - DAC0 I data
M1 - DAC0 Q data
M2- DAC1 I data
M3 - DAC1 Q data
1 Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0.