| SLA Status | Assignee | Support Status |
|---|---|---|
| SLA Closed. | Open | |
AD9173
Recommended for New Designs
The AD9173 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates to 12.6 GSPS. The device features an 8...
Datasheet
AD9173 on Analog.com
HMC7044
Not Recommended for New Designs
The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise...
Datasheet
HMC7044 on Analog.com
AD9172
Recommended for New Designs
The AD9172 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates to 12.6 GSPS. The device features an 8...
Datasheet
AD9172 on Analog.com
Hey y'all,
I'm trying to configure the AD9173 for startup on a custom board we've designed, but I'm having trouble getting the SERDES PLL to lock. The board schematic was copied/pasted from the AD9173 EVAL board, including the HMC7044 chip. The only difference is we are using a 100 MHz crystal reference and VCXO for the HMC7044, and the SERDES lanes come directly from a Xilinx Kintex-7 FPGA.
I've managed to configure the HMC7044 as needed. It outputs a 160 MHz clock signal into the AD9173 CLKIN+/- ports. I can also successfully read/write AD9173 registers via the SPI bus.
For the time being, I am trying to run in subclass 0 in NCO-only mode, by loading the DC amplitude into the main datapath NCO. Eventually I'd like to run subclass 1 using the SYSREF, but we can deal with that another day 
.
My issue comes during the startup sequence, which starts on page 66 of the Rev. A datasheet. Everything up until the JESD204B SERDES Required Interface Setup (Table 56) goes smoothly, i.e. the DAC PLL locks, the DLLs lock, and the FTW acknowledge bits are high. However, once I have to power up the SERDES circuitry block by writing 0x00 to register 0x200, a bunch of things go wrong.
For instance, I am running single link in mode 3 with a main datapath interpolation of 6 and a channel interpolation of 3. So I write 0x03 to register 0x110, and 0x63 to 0x111. Before powering up the SERDES circuitry block, I readback these registers and obtain the correct values. However after I power up the SERDES circuitry block (write 0x00 to register 0x200), I get readback values 0x110=0xA0, and 0x111=84. Register 0x300 reads back 0x09, which implies that I've set it up for dual-link even though I set it up for single link earlier by setting 0x300 to 0x01. How does this make any sense? My JESD parameters and PLL setup are shown below. I've also attached a text file with my start-up register sequence. It's heavily commented to make this process easier.
Another question related to the startup deals with register 0x085. The start-up sequence only says you have to set 0x085 to 0x13 at the end of the sequence. However the register details imply that you have to set this register to 0x12 at the start of the sequence, and 0x01 at the end. Which is it?
Thanks so much for any help! I'm happy to share more info if it helps.
Mashrur
JESD Parameters:
| Link Mode | Single |
| JESD Mode | 3 |
| L | 2 |
| M | 2 |
| F | 2 |
| S | 1 |
| NP | 16 |
| N | 16 |
| K | 32 |
| HD | 1 |
| Scrambling | On |
| Chan interp | 3 |
| Main datapath interp | 6 |
| Total interp | 18 |
| Data rate (MHz) | 320 |
| fDAC (GHz) | 5.76 |
| Lane rate (GSps) | 6.4 |
PLL Setup:
Startup sequence:
% ----- Power up and required register writes: 0x000: 0x81 % softreset 0x000: 0x00 % take out of reset 0x001: 0x80 % single instruction SPI 0x085: 0x12 % Set to 0x12 at start of start-up sequence 0x091: 0x00 % power up clock receiver 0x206: 0x01 % take PHYs out of reset 0x705: 0x01 % enable boot loader % PAUSE 10ms AFTER PREVIOUS STEP. Can readback reg 0x705[1]==1 0x09000 % power on DACs and bias circuitry % ----- DAC PLL Config 0x095: 0x00 % 0x00 uses internal PLL 0x790: 0x00 % 0x00 uses internal PLL 0x791: 0x00 % 0x00 uses internal PLL 0x796: 0xE5 % DAC PLL required write 0x7A0: 0xBC % DAC PLL required write 0x794: 0x08 % DAC PLL charge pump current, 0x04-0x10. 0x08 midrange. 0x797: 0x10 % DAC PLL required write 0x797: 0x20 % DAC PLL required write 0x798: 0x10 % DAC PLL required write 0x7A2: 0x7F % DAC PLL required write % PAUSE 100ms AFTER PREVIOUS STEP 0x799: 0x09 % DAC PLL N-divider. N = 9 0x793: 0x18 % DAC PLL M-divider. M = 1 0x094: 0x01 % PLL VCO output divider. Divide by 2. 0x792: 0x02 % Reset VCO 0x792: 0x00 % Take VCO out of reset % PAUSE 100ms AFTER PREVIOUS STEP % Can read back reg 0x075B[0]==1 to confirm PLL lock % ----- DLL Configuration 0x0C0: 0x00 % Power up delay line 0x0DB: 0x00 0x0DB: 0x01 % Update DLL settings to circuitry 0x0DB: 0x00 0x0C1: 0x68 % DLL search mode. fDAC>4.5GHz, so set to 0x68 0x0C1: 0x69 % DLL search mode. fDAC>4.5GHz, so set to 0x69 0x0C7: 0x01 % Enable DLL read status % Can read back reg 0x00C3[0]==1 to confirm DLL lock % ----- Calibration 0x050: 0x2A % Optimized calibration setting register write. 0x061: 0x68 % Required calibration control register write. 0x051: 0x82 % Optimized calibration setting register write. 0x051: 0x83 % Required calibration control register write. 0x081: 0x03 % Required calibration control register write. % ----- JESD204B Mode Setup 0x100: 0x00 % power up digital datapath clocks when internal clocks are stable 0x110: 0x03 % JESD single link, mode 3 0x111: 0x63 % DP interp = 6. Chan interp = 3. 0x084: 0x01 % SYSREF AC coupled, SYSREF receiver off for subclass 0 0x312: 0x00 % SYNCOUT error duration (?), left default value 0x300: 0x01 % single link, link 0 (QBD0), enable single link 0x475: 0x09 % soft reset JESD204B quad-byte deframer 0x453: 0x81 % enable scrambing. L-1=1. 0x454: 0x01 % F-1=1. 0x455: 0x1F % K-1=31. 0x456: 0x01 % M-1=1. 0x457: 0x0F % N-1=15. 0x458: 0x0F % subclass 0. NP-1=15 0x459: 0x20 % JESD204B. S-1=0. 0x475: 0x01 % bring JESD204B quad-byte deframer out of reset % ----- Channel Datapath setup: Digital gain and channel NCOs % Channel 0 0x008: 0x01 % Channel 0 page 0x146: 0x00 % Gain LSB. Gain = 1, gain code = 2048. 0x147: 0x08 % Gain MSB. % **************** DC test mode: ************************ 0x130: 0x40 % enable channel NCO. 0x148: 0x00 % DC test tone amplitude [ 7:0] 0x149: 0x5A % DC test tone amplitude [15:8] % ******************************************************* % DDS or NCO phase, frequency, etc. all default 0 0x131: 0x01 % update NCO & FTW words % Channel 1-5 0x008: 0x3E % Channel 1-5 page 0x146: 0x00 % Gain LSB. Gain = 0, gain code = 0. 0x147: 0x00 % Gain MSB. 0x130: 0x00 % disable channel NCO % DDS or NCO phase, frequency, etc. all default 0 0x131: 0x01 % update channel NCO & FTW words % ----- Main DAC Datapath Setup 0x008: 0x40 % DAC0 page 0x1E6: 0x02 % Enable DC input into calibration DDS 0x112: 0x0C % enable NCO and NCO modulus % For 800 MHz carrier and 5.76 GHz DAC, use following params: % X: 0x238E38E38E38 % B: 0x40 % A: 0x39 0x114: 0x38 % X: DDSM_FTW[ 7: 0] 0x115: 0x8E % X: DDSM_FTW[15: 8] 0x116: 0xE3 % X: DDSM_FTW[23:16] 0x117: 0x38 % X: DDSM_FTW[31:24] 0x118: 0x8E % X: DDSM_FTW[39:32] 0x119: 0x23 % X: DDSM_FTW[47:40] 0x124: 0x40 % B: DDSM_ACC_MODULUS[ 7: 0] 0x125: 0x00 % B: DDSM_ACC_MODULUS[15: 8] 0x126: 0x00 % B: DDSM_ACC_MODULUS[23:16] 0x127: 0x00 % B: DDSM_ACC_MODULUS[31:24] 0x128: 0x00 % B: DDSM_ACC_MODULUS[39:32] 0x129: 0x00 % B: DDSM_ACC_MODULUS[47:40] 0x12A: 0x39 % A: DDSM_ACC_DELTA[ 7: 0] 0x12B: 0x00 % A: DDSM_ACC_DELTA[15: 8] 0x12C: 0x00 % A: DDSM_ACC_DELTA[23:16] 0x12D: 0x00 % A: DDSM_ACC_DELTA[31:24] 0x12E: 0x00 % A: DDSM_ACC_DELTA[39:32] 0x12F: 0x00 % A: DDSM_ACC_DELTA[47:40] 0x113: 0x01 % update datapath NCO & FTW words % ----- JESD204B SERDES Required Interface Setup 0x240: 0xAA % EQ settings 0x241: 0xAA % EQ settings 0x242: 0x55 % EQ settings 0x243: 0x55 % EQ settings 0x244: 0x1F % EQ settings 0x245: 0x1F % EQ settings 0x246: 0x1F % EQ settings 0x247: 0x1F % EQ settings 0x248: 0x1F % EQ settings 0x249: 0x1F % EQ settings 0x24A: 0x1F % EQ settings 0x24B: 0x1F % EQ settings 0x201: 0x00 % Enable all PHY lanes for now 0x203: 0x01 % single link SYNCOUT driver 0x253: 0x01 % SYNCOUT0 LVDS driver 0x254: 0x01 % SYNCOUT1 LVDS driver 0x210: 0x16 % SERDES required register write. 0x216: 0x05 % SERDES required register write. 0x212: 0xFF % SERDES required register write. 0x212: 0x00 % SERDES required register write. 0x210: 0x87 % SERDES required register write. 0x216: 0x11 % SERDES required register write. 0x213: 0x01 % SERDES required register write. 0x213: 0x00 % SERDES required register write. 0x200: 0x00 % Power up the SERDES circuitry blocks. **** PROBLEMATIC LINE ***** % PAUSE 100ms 0x210: 0x86 % SERDES required register write. 0x216: 0x40 % SERDES required register write. 0x213: 0x01 % SERDES required register write. 0x213: 0x00 % SERDES required register write. 0x210: 0x86 % SERDES required register write. 0x216: 0x00 % SERDES required register write. 0x213: 0x01 % SERDES required register write. 0x213: 0x00 % SERDES required register write. 0x210: 0x87 % SERDES required register write. 0x216: 0x01 % SERDES required register write. 0x213: 0x01 % SERDES required register write. 0x213: 0x00 % SERDES required register write. 0x280: 0x05 % SERDES required register write. 0x280: 0x01 % Start up SERDES PLL circuitry blocks and initiate SERDES PLL calibration. % Can read back reg 0x0281[0]==1 to confirm SERDES PLL lock % ----- Transport Layer Setup, Synchronization, and Enable Links % 0x0308-0x030B is crossbar setup. Leave at default 0x306: 0x0C % Subclass1 required write 0x307: 0x0C % Subclass1 required write 0x304: 0x00 % LMFC link0 delay 0x03B: 0xF1 % Enable sync logic 0x03A: 0x00 % Set up sync for monitor mode 0x03A: 0x02 % Set up sync for one-shot sync mode 0x300: 0x01 % single link % ----- Cleanup Registers 0x085: 0x01 % Set to 0x01 at end of start-up sequence 0x008: 0xC0 % Page all main DACs for TXEN control update 0x581: 0x00 % disable PA soft off features 0x582: 0x00 % disable PA soft on features 0x596: 0x0C % SPI turn on TXENx feature
