First, I believe that the CGS and Good Checksum check lights in ACE are backwards and would probably be worth fixing.
Second, While I'm getting ILAS and data at at DAC0, my received Lane IDs and JESD Version doesn't match what is set on the DAC. For reference, I am using a Xilinx FPGA and their JESD204 IP block.
For the lane IDs, since DAC side I only set Lane 0, I made the assumption Lanes 1-7 get set automatically and sequentially from there. That said the following table shows the expected LID per lane and the received LIDs from on the DAC.
Now I've set all the LIDs in the JESD204 IP block but their default values should be the same as what's expected on the DAC. Do you have any ideas for the misinterpretation?
For the JESD version, I have the DAC set to JESD204B by writing 0b001 to JESDV under register 0x0459, however my received JESDV is 0b110. My first hunch was that somehow this got inverted, but if it did, that would be the case with all other link parameters which isn't the case.
All of this then begs the question, how did were we able to achieve ILAS without these matching?
Almost as soon as I asked this question I figured out my answer: I looked over the crossbar functionality that can change the routing of the physical lanes to the various logical lanes.
I was compensating for the SERDES inputs and FMC's C2M pins not matching by adjusting my pin mapping on my FPGA, not realizing that was already being accounted for on the DAC with the crossbar. I now have Good Checksums on all lanes and Lane IDs and the JESDV (inverted as lanes 0-3 needed inverted but lane 0 was being routed to lane 5) all match the expected values.
That said, I still don't understand why ILAS was being achieved with this error being present, but I suppose now it doesn't really matter.