I am using the AD9152-FMC-EBZ eval board. I am configuring the DAC (AD9152) in mode 7 (PClock Rate = FrameClock Rate = Data Rate = 250 Mhz). I am using the external PLL (AD9516) to supply the SYSREF (using subclass 1) and using a signal generator to provide the DAC with the DACCLK (not using the REFCLK to gen the DACCLK internally). I am using the following values to program the DAC over SPI (following the device setup guide on page 24 of the datasheet):
#table 15 - power-up and DAC initialization./dac_write 0x0000 0xBD #soft reset./dac_write 0x0000 0x3C #de-assert reset, set 4-lane spi./dac_write 0x0011 0x00./dac_write 0x0080 0x04./dac_write 0x0081 0x00 #subclass 1./dac_write 0x01CD 0xD8./dac_write 0x0000 0x18
#table 16 - SERDES PLL configuration./dac_write 0x0284 0x62./dac_write 0x0285 0xC9./dac_write 0x0286 0x0E./dac_write 0x0287 0x12./dac_write 0x028A 0x2B./dac_write 0x028B 0x00./dac_write 0x0290 0x89./dac_write 0x0291 0x4C./dac_write 0x0294 0x24./dac_write 0x0296 0x03./dac_write 0x0297 0x0D./dac_write 0x0299 0x02./dac_write 0x029A 0x8E./dac_write 0x029C 0x2A./dac_write 0x029F 0x7E./dac_write 0x02A0 0x06
#table 17 - more DAC PLL configurations./dac_write 0x008D 0x7B./dac_write 0x01B0 0x00./dac_write 0x01B9 0x24./dac_write 0x01BC 0x0D./dac_write 0x01BE 0x02./dac_write 0x01BF 0x8E./dac_write 0x01C0 0x2A./dac_write 0x01C4 0x7E./dac_write 0x01C1 0x2C
# #table 18 skipped since not using DAC PLL (optional DAC PLL settings)
# #table 19 - Digital Datapath Settings./dac_write 0x0112 0x00./dac_write 0x0110 0x00
#table 20 - Transport Layer Settings./dac_write 0x0200 0x00 #power up jesd interface./dac_write 0x0201 0x0E #power down jesd lanes./dac_write 0x0300 0x01 #checksum mode and link enable./dac_write 0x0450 0x00 #DID./dac_write 0x0451 0x00 #BID./dac_write 0x0452 0x00 #LID./dac_write 0x0453 0x00 #scrambling./dac_write 0x0454 0x03 #frames-1./dac_write 0x0455 0x0F #multiframe-1./dac_write 0x0456 0x01 #DACs-1./dac_write 0x0457 0x0F #samples-1./dac_write 0x0458 0x2F #subclass 1./dac_write 0x0459 0x20 #JESD204B./dac_write 0x045A 0x00 #high density./dac_write 0x045D 0x33 #checksum value #33./dac_write 0x046C 0x01 #deskew lanes./dac_write 0x0476 0x04 #octets per frame./dac_write 0x047D 0x01 #enable all lanes
#table 21 - Device Configurations andl Physical Layer Settings./dac_write 0x02A7 0x01 #autotune phy terminators./dac_write 0x0314 0x01./dac_write 0x0230 0x29./dac_write 0x0206 0x00./dac_write 0x0206 0x01./dac_write 0x0289 0x04./dac_write 0x0280 0x01./dac_write 0x0268 0x22
#table 22 - Data Link Layer Settings./dac_write 0x0301 0x01 #subclass 1./dac_write 0x0304 0x0D #LMFCdel./dac_write 0x0306 0x06 #LMFCvar./dac_write 0x003A 0x02 #sync mode./dac_write 0x003A 0x82 #enable sync machine./dac_write 0x003A 0xC2 #arm the sync machine./dac_write 0x0308 0x08 #lane mapping 1 and 2./dac_write 0x0309 0x1A #lane maping 3 and 4./dac_write 0x0334 0x01 #invert lane polarity (lane 0 polarity swapped on eval board)./dac_write 0x0300 0x01 #link enable
After the DAC is programmed the JESD tx block in the FPGA starts the CGS then once the DAC recognizes the 4 /K/ chars it asserts SYNCOUT and the ILA sequence begins. The issue is about 75% of the way through the ILAS the DAC asserts the SYNCOUT signal (Picture below) and then the CGS is sent again and then the ILAS is sent again... etc. This infinitely loops. When I check the CODEGRPSYNCFLAG (Register 0x470) it oscillates between 0x00 and 0x01 so the CGS is seen by the DAC. The FRAMESYNCFLAG (Register 0x471) also oscillates between 0x00 and 0x01. However, the GOODCHKSUMFLG (Register 0x472) and INITIALLANESYNC (Register 0x473) are always 0x00.
A logic analyzer on the FPGA shows the SYNC dropping low in the middle of multiframe 2 in the ILAS:
So does this appear to be an ILAS issue or is there something else I am missing?
If there is any additional information necessary I would be happy to provide it.
Please check that both ends of the link are configured the same and also the polarity of SYNC~. Also, consult the JESD204B Link Debug guide.
Hello, thank you for the reply. I checked to make sure both ends are configured correctly and the sync polarity is correct. I switched to mode 4 (following the example start up sequence in the AD9152 datasheet) to see if I incorrectly programmed the registers but the same behavior is still present. However, I noticed the disparity and unexpected control error counters are saturating. Does this indicate there may be an issue with the channel?
Also, the CHIPGRADE register on the AD9152 I have is 0x07 so I am using REV. 0 of the datasheet.
It seems the time between the rising edge of SYNC and the start of ILAS is longer than the length of a multiframe. Shouldn't the ILAS start on the next LMFC ?
Hi, I seem to be having the same issue as EBenson939. Any additional advice/direction would be greatly appreciated.
Let's try bringing up the link in subclass 0 (do not "arm" ore even apply the sysref). It would be helpful to provide two chipscope plots - an additional one zoomed in to show what the data looks like prior to sync being re-asserted during ILAS. Also, check the link status registers in the AD9152 - 0x470-0x473